From: Alif Zakuan Yuslaimi <[email protected]>

Add DRAM size checking compare between size from device tree and actual
hardware.

Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.

get_ram_size() uses size from device tree. So, it has consistency with
other device families.

New Kconfig is introduced to enable this implementation only on the default
CycloneV board as this will increase the SPL size which will exceed some
Gen5 devices' SPL size limit.

Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
---

Changes in v3:
- Move the bdata declaration and gd->bd = &bdata assignment from spl_gen5.c
  in patch 3 into this patch, making this patch self-contained

Changes in v2:
- DRAM size checking is set as optional via Kconfig and defaulted on only
  for the reference Arria10/CycloneV boards to avoid SPL overflows on
  size-limited Gen5 defconfigs.

 arch/arm/mach-socfpga/Kconfig    |  9 +++++++++
 arch/arm/mach-socfpga/spl_gen5.c | 11 +++++++++++
 drivers/ddr/altera/sdram_gen5.c  | 27 +++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index fb98b647442..b814e034ecd 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -6,6 +6,12 @@ config ERR_PTR_OFFSET
 config NR_DRAM_BANKS
        default 1
 
+config SOCFPGA_DRAM_SIZE_CHECK
+       bool "Enable DRAM size checking for safety"
+       help
+        Compares device tree DRAM size with actual hardware. Hangs on
+        oversized claim.
+
 config SOCFPGA_SECURE_VAB_AUTH
        bool "Enable boot image authentication with Secure Device Manager"
        depends on ARCH_SOCFPGA_AGILEX || ARCH_SOCFPGA_N5X || \
@@ -111,6 +117,9 @@ config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
 config ARCH_SOCFPGA_CYCLONE5
        bool
        select ARCH_SOCFPGA_GEN5
+       select SOCFPGA_DRAM_SIZE_CHECK if !TARGET_SOCFPGA_TERASIC_SOCKIT \
+         && !TARGET_SOCFPGA_EBV_SOCRATES && \
+         !TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config ARCH_SOCFPGA_GEN5
        bool
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 08b756db2ca..a9825173189 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -6,6 +6,7 @@
 #include <hang.h>
 #include <init.h>
 #include <log.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -24,6 +25,12 @@
 #include <dm/uclass.h>
 #include <linux/bitops.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)
+static struct bd_info bdata __attribute__ ((section(".data")));
+#endif
+
 u32 spl_boot_device(void)
 {
        const u32 bsel = readl(socfpga_get_sysmgr_addr() +
@@ -143,6 +150,10 @@ void board_init_f(ulong dummy)
        /* enable console uart printing */
        preloader_console_init();
 
+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)
+       gd->bd = &bdata;
+#endif
+
        ret = uclass_get_device(UCLASS_RAM, 0, &dev);
        if (ret) {
                debug("DRAM init failed: %d\n", ret);
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 3c79bb11802..1c3c70ea8ae 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -5,6 +5,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <div64.h>
+#include <hang.h>
 #include <init.h>
 #include <log.h>
 #include <ram.h>
@@ -15,6 +16,7 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/system_manager.h>
 #include <asm/bitops.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <dm/device_compat.h>
 
@@ -22,6 +24,8 @@
 
 #ifdef CONFIG_XPL_BUILD
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct altera_gen5_sdram_priv {
        struct ram_info info;
 };
@@ -604,8 +608,31 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
        sdram_size = sdram_calculate_size(sdr_ctrl);
        debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 
+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)
+       /* setup the dram info within bd */
+       dram_init_banksize();
+
+       if (sdram_size != gd->bd->bi_dram[0].size) {
+               printf("DDR: Warning: DRAM size from device tree (%lu MiB)\n",
+                      (ulong)(gd->bd->bi_dram[0].size >> 20));
+               printf(" mismatch with hardware (%lu MiB).\n",
+                      (ulong)(sdram_size >> 20));
+       }
+
+       if (gd->bd->bi_dram[0].size > sdram_size) {
+               printf("DDR: Error: DRAM size from device tree is greater\n");
+               printf(" than hardware size.\n");
+               hang();
+       }
+#endif
+
        /* Sanity check ensure correct SDRAM size specified */
+#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)
+       if (get_ram_size(0, gd->bd->bi_dram[0].size) !=
+           gd->bd->bi_dram[0].size) {
+#else
        if (get_ram_size(0, sdram_size) != sdram_size) {
+#endif
                puts("SDRAM size check failed!\n");
                goto failed;
        }
-- 
2.43.7

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