On Tue, May 12, 2026 at 2:50 PM <[email protected]> wrote: > > From: Alif Zakuan Yuslaimi <[email protected]> > > Add DRAM size checking compare between size from device tree and actual > hardware. > > Trigger hang if DRAM size from device tree is greater than actual hardware. > Display warning message if DRAM size mismatch between device tree and > actual hardware. > > get_ram_size() uses size from device tree. So, it has consistency with > other device families. > > New Kconfig is introduced to enable this implementation only on the default > CycloneV board as this will increase the SPL size which will exceed some > Gen5 devices' SPL size limit. > > Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> > --- > > Changes in v3: > - Move the bdata declaration and gd->bd = &bdata assignment from spl_gen5.c > in patch 3 into this patch, making this patch self-contained > > Changes in v2: > - DRAM size checking is set as optional via Kconfig and defaulted on only > for the reference Arria10/CycloneV boards to avoid SPL overflows on > size-limited Gen5 defconfigs. > > arch/arm/mach-socfpga/Kconfig | 9 +++++++++ > arch/arm/mach-socfpga/spl_gen5.c | 11 +++++++++++ > drivers/ddr/altera/sdram_gen5.c | 27 +++++++++++++++++++++++++++ > 3 files changed, 47 insertions(+)
Tested-by: Brian Sune <[email protected]> Testing environment: - Latest repository - Custom board 2G max capacity SoCFPGA Cyclone V can handle. - SDMMC Boot Both cold warm reset shows no issue: Boot log: U-Boot SPL 2026.07-rc2-00016-g36d4c6535808-dirty (May 14 2026 - 08:24:01 +0800) DDRCAL: Scrubbing ECC RAM (2048 MiB). DDRCAL: SDRAM-ECC initialized success with 1053 ms Trying to boot from MMC1 U-Boot 2026.07-rc2-00016-g36d4c6535808-dirty (May 14 2026 - 08:24:01 +0800) Thanks, Brian
