From: Peng Fan <[email protected]> The U-Boot copy of the board device trees for this board is almost same as the ones in dts/upstream except some differences in display which not impact U-Boot as of now, so switch to the board to OF_UPSTREAM, by dropping the U-Boot copies and selecting OF_UPSTREAM.
There are some changes in imx8mm-tqma8mqml.dtsi regarding sdhc2 supply, select DM_PMIC_PCA9450, DM_REGULATOR_PCA9450 and SPL_DM_REGULATOR_PCA9450 to avoid breaking sd. Signed-off-by: Peng Fan <[email protected]> --- arch/arm/dts/Makefile | 1 - arch/arm/dts/imx8mm-phg.dts | 266 ----------------------------- arch/arm/dts/imx8mm-tqma8mqml.dtsi | 341 ------------------------------------- arch/arm/mach-imx/imx8m/Kconfig | 1 + configs/imx8mm_phg_defconfig | 5 +- 5 files changed, 5 insertions(+), 609 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dacea5487c6..acf1a1b8495 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -875,7 +875,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-data-modul-edm-sbc.dtb \ imx8mm-mx8menlo.dtb \ - imx8mm-phg.dtb \ imx8mq-cm.dtb \ imx8mp-data-modul-edm-sbc.dtb \ imx8mp-dhcom-som-overlay-rev100.dtbo \ diff --git a/arch/arm/dts/imx8mm-phg.dts b/arch/arm/dts/imx8mm-phg.dts deleted file mode 100644 index e9447738b10..00000000000 --- a/arch/arm/dts/imx8mm-phg.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Fabio Estevam <[email protected]> - */ - -/dts-v1/; - -#include "imx8mm-tqma8mqml.dtsi" - -/ { - model = "Cloos i.MX8MM PHG board"; - compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; - - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc2; - }; - - chosen { - stdout-path = &uart2; - }; - - beeper { - compatible = "gpio-beeper"; - pinctrl-0 = <&pinctrl_beeper>; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - led-0 { - label = "status1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "status2"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "status3"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - label = "run"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - - led-4 { - label = "powerled"; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg_vbus_ctrl>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbphynop1 { - power-domains = <&pgc_otg1>; -}; - -&usbphynop2 { - power-domains = <&pgc_otg2>; -}; - -&usbotg1 { - dr_mode = "host"; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - no-mmc; - no-sdio; - sd-uhs-sdr104; - sd-uhs-ddr50; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_beeper: beepergrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14 - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14 - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14 - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14 - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14 - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_otg_vbus_ctrl: otgvbusctrlgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-tqma8mqml.dtsi b/arch/arm/dts/imx8mm-tqma8mqml.dtsi deleted file mode 100644 index f649dfacb4b..00000000000 --- a/arch/arm/dts/imx8mm-tqma8mqml.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2020-2021 TQ-Systems GmbH - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mm.dtsi" - -/ { - model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; - compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; - - memory@40000000 { - device_type = "memory"; - /* our minimum RAM config will be 1024 MiB */ - reg = <0x00000000 0x40000000 0 0x40000000>; - }; - - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* identical to buck4_reg, but should never change */ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - /* 640 MiB */ - size = <0 0x28000000>; - /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ - alloc-ranges = <0 0x40000000 0 0x78000000>; - linux,cma-default; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <84000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&gpu_2d { - status = "okay"; -}; - -&gpu_3d { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - sensor0: temperature-sensor-eeprom@1b { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; - reg = <0x1b>; - }; - - pca9450: pmic@25 { - compatible = "nxp,pca9450a"; - reg = <0x25>; - - /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ - pinctrl-0 = <&pinctrl_pmic>; - pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - - regulators { - /* V_0V85_SOC: 0.85 */ - buck1_reg: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - /* VDD_ARM */ - buck2_reg: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - regulator-ramp-delay = <3125>; - }; - - /* V_0V85_GPU / DRAM / VPU */ - buck3_reg: BUCK3 { - regulator-name = "BUCK3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - /* VCC3V3 -> VMMC, ... must not be changed */ - buck4_reg: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ - buck5_reg: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V1 -> RAM, ... must not be changed */ - buck6_reg: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V8_SNVS */ - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_0V8_SNVS */ - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V8_ANA */ - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_0V9_MIPI */ - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VCC SD IO - switched using SD2 VSELECT */ - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - - pcf85063: rtc@51 { - compatible = "nxp,pcf85063a"; - reg = <0x51>; - quartz-load-femtofarads = <7000>; - }; - - eeprom1: eeprom@53 { - compatible = "nxp,se97b", "atmel,24c02"; - read-only; - reg = <0x53>; - pagesize = <16>; - }; - - eeprom0: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <32>; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc1v8>; - status = "okay"; -}; - -/* - * Attention: - * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR - * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. - */ -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_flexspi: flexspigrp { - fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>, - <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, - <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, - <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, - <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, - <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>, - <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>, - <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, - <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, - <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, - <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, - <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, - <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, - /* option USDHC3_RESET_B not defined, only in RM */ - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, - <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, - <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, - <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, - <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, - <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, - /* option USDHC3_RESET_B not defined, only in RM */ - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, - <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, - <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, - <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, - <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, - <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, - /* option USDHC3_RESET_B not defined, only in RM */ - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index aa8783e971b..af3e3d5f0c3 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -139,6 +139,7 @@ config TARGET_IMX8MM_PHG select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_VENICE bool "Support Gateworks Venice iMX8M Mini module" diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index 8fbe0e049e6..c99b8e22bac 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phg" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phg" CONFIG_TARGET_IMX8MM_PHG=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y @@ -90,8 +90,11 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_SPL_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -- 2.51.0
