Add a UCLASS_CLK driver matching the Linux DT binding documented at Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml, a fixed-rate oscillator whose output is enabled by toggling a regulator supply. The optional enable-gpios variant is not implemented.
The first user in U-Boot will be rk3588-rock-5-itx, where the PCIe3 ports reference a PI6C 100MHz oscillator declared with this compatible and pcie_dw_rockchip currently fails clk_get_by_index() with -ENODEV on every boot since v2026.04. Suggested-by: Jonas Karlman <[email protected]> Signed-off-by: Daniele Briguglio <[email protected]> --- drivers/clk/Kconfig | 9 +++++ drivers/clk/Makefile | 1 + drivers/clk/clk-gated-fixed.c | 84 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c2da7b393..0c2f4698e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -94,6 +94,15 @@ config CLK_COMPOSITE_CCF Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] composite code in U-Boot's clock driver. +config CLK_GATED_FIXED + bool "Regulator-gated fixed-rate clock driver" + depends on CLK && DM_REGULATOR + help + Enable this option to add a driver for fixed-rate clocks whose + output is gated by a regulator supply, described in the device + tree with the "gated-fixed-clock" compatible. Typical use is + external PCIe reference clock generators on Rockchip boards. + config CLK_GPIO bool "GPIO-controlled clock gate driver" depends on CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 5f0c0d8a5..338ddc029 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_$(PHASE_)CLK) += clk_fixed_factor.o obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-fixed-factor.o obj-$(CONFIG_$(PHASE_)CLK_COMPOSITE_CCF) += clk-composite.o +obj-$(CONFIG_$(PHASE_)CLK_GATED_FIXED) += clk-gated-fixed.o obj-$(CONFIG_$(PHASE_)CLK_GPIO) += clk-gpio.o obj-$(CONFIG_$(PHASE_)CLK_STUB) += clk-stub.o diff --git a/drivers/clk/clk-gated-fixed.c b/drivers/clk/clk-gated-fixed.c new file mode 100644 index 000000000..d52f278d7 --- /dev/null +++ b/drivers/clk/clk-gated-fixed.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2026 Daniele Briguglio <[email protected]> + * + * Clock driver for a fixed-rate oscillator gated by a regulator + * supply (Linux DT binding "gated-fixed-clock"). + */ + +#define LOG_CATEGORY UCLASS_CLK + +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <power/regulator.h> +#include <dm/device_compat.h> + +struct clk_gated_fixed_priv { + struct udevice *supply; + ulong rate; +}; + +static int clk_gated_fixed_enable(struct clk *clk) +{ + struct clk_gated_fixed_priv *priv = dev_get_priv(clk->dev); + + return regulator_set_enable_if_allowed(priv->supply, true); +} + +static int clk_gated_fixed_disable(struct clk *clk) +{ + struct clk_gated_fixed_priv *priv = dev_get_priv(clk->dev); + + return regulator_set_enable_if_allowed(priv->supply, false); +} + +static ulong clk_gated_fixed_get_rate(struct clk *clk) +{ + struct clk_gated_fixed_priv *priv = dev_get_priv(clk->dev); + + return priv->rate; +} + +static const struct clk_ops clk_gated_fixed_ops = { + .enable = clk_gated_fixed_enable, + .disable = clk_gated_fixed_disable, + .get_rate = clk_gated_fixed_get_rate, +}; + +static int clk_gated_fixed_probe(struct udevice *dev) +{ + struct clk_gated_fixed_priv *priv = dev_get_priv(dev); + u32 rate; + int ret; + + ret = dev_read_u32(dev, "clock-frequency", &rate); + if (ret) { + dev_err(dev, "missing clock-frequency: %d\n", ret); + return ret; + } + priv->rate = rate; + + ret = device_get_supply_regulator(dev, "vdd-supply", &priv->supply); + if (ret) { + dev_err(dev, "failed to get vdd-supply: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct udevice_id clk_gated_fixed_match[] = { + { .compatible = "gated-fixed-clock" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gated_fixed_clock) = { + .name = "gated_fixed_clock", + .id = UCLASS_CLK, + .of_match = clk_gated_fixed_match, + .probe = clk_gated_fixed_probe, + .priv_auto = sizeof(struct clk_gated_fixed_priv), + .ops = &clk_gated_fixed_ops, +}; -- 2.47.3
