Hi Alif,
On 18/5/2026 9:12 am, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]> This patch set updates the boot support for the Altera SoCFPGA Stratix10 platform in U-Boot. The changes include: 1. Board-specific configurations and setup required to enable Stratix10 multiboot operation in U-Boot. 2. Integration of cache coherency unit (CCU) initialization routine, including CCU conguration in DT. 3. Clock, firewall (configured in DT), SMMU, low level initialization specific to Stratix10. 4. Refactor of the Stratix10 clock driver and targeted updates to the MMC driver for compatibility with the refactored clock driver. This patch set has been tested on Stratix10 devkit with QSPI boot (UBI/UBIFS), SDMMC boot and RAM boot (TFTP & ARM DS debugger). Changes in v3: - Removed fdt-2 under &images node and board-2 under &board_config node as socfpga_stratix10_socdk_emmc.dts is not yet available - Regenerate defconfig with make savedefconfig - SPDX-License-Identifier format correction in board/altera/stratix10-socdk/Makefile - Retain Intel Corporation copyright notices - Add clk_get_l4_main_clk_hz() for STRATIX10_L4_MAIN_CLK clock rate Changes in v2: - Cleaned up git merge artifact - Cleaned up cdns,read-delay parameter for spi node - Cleaned up duplicated /delete-node/ kernel in binman node - Implement using real hardware clock source frequency following Agilex clock driver - Commit message improvement Alif Zakuan Yuslaimi (9): arch: arm: dts: stratix10: Switch to using upstream Linux DT config configs: stratix10: Combine defconfig for all boot flashes arm: socfpga: Move firmware register settings from source code to device tree arm: socfpga: Update Stratix10 SPL data save and restore implementation arm: socfpga: s10: Enable system manager driver for Stratix10 ddr: altera: soc64: Add secure region support for ATF flow clk: s10: Refactor S10 clock driver mmc: socfpga_dw_mmc: Exclude S10 from legacy clkmgr address retrieval spl: s10: Enhance watchdog support in SPL for Stratix 10 MAINTAINERS | 2 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 313 +++++++++ arch/arm/dts/socfpga_stratix10.dtsi | 430 ------------ .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 119 +++- arch/arm/dts/socfpga_stratix10_socdk.dts | 143 ---- arch/arm/mach-socfpga/Kconfig | 2 + arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/clock_manager_s10.c | 448 ++----------- .../include/mach/clock_manager_s10.h | 175 +---- arch/arm/mach-socfpga/misc.c | 6 +- arch/arm/mach-socfpga/spl_s10.c | 70 +- board/altera/stratix10-socdk/Makefile | 6 + board/altera/stratix10-socdk/socfpga.c | 12 + configs/socfpga_stratix10_atf_defconfig | 90 --- configs/socfpga_stratix10_defconfig | 69 +- drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-s10.c | 616 ++++++++++++++++++ drivers/clk/altera/clk-s10.h | 203 ++++++ drivers/ddr/altera/sdram_s10.c | 60 +- drivers/mmc/socfpga_dw_mmc.c | 6 +- 21 files changed, 1408 insertions(+), 1367 deletions(-) delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts create mode 100644 board/altera/stratix10-socdk/Makefile create mode 100644 board/altera/stratix10-socdk/socfpga.c delete mode 100644 configs/socfpga_stratix10_atf_defconfig create mode 100644 drivers/clk/altera/clk-s10.c create mode 100644 drivers/clk/altera/clk-s10.h
Looks good overall for master, OF_UPSTREAM + DT firewall + clk DM is the right direction. Please rebase on current master, fix reset_flag(u32 flag) in P4 to match spl_data.c, and note SDMMC boot validation after defconfig merge. Happy to Ack v4 after that.
Best regards, Tien Fong
