Hi Tien Fong,
On 3/6/2026 3:45 pm, Chee, Tien Fong wrote:
Hi Alif,
On 18/5/2026 9:12 am, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]>
Watchdog should be primed before longer, failure-prone steps such as
firewall, SDRAM or QSPI initialization so that if a hang occurs in one of
those steps, it is able to trigger a reset.
Switch from the legacy hw_watchdog_init() path to the driver-model WDT
(initr_watchdog()). This requires clocks and reset to be valid for
the L4 watchdog block, and so it must run after the clock manager
(uclass_get_device(UCLASS_CLK)) succeeds.
Enabling watchdog immediately after clock init keeps watchdog coverage as
early as possible.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
---
(no changes since v2)
Changes in v2:
- Commit message improvement
arch/arm/mach-socfpga/spl_s10.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/
spl_s10.c
index ace029557f3..588dca4fcd3 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -18,7 +18,7 @@
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-#include <watchdog.h>
+#include <wdt.h>
#include <dm/uclass.h>
u32 reset_flag(void)
@@ -54,13 +54,6 @@ void board_init_f(ulong dummy)
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
-#ifdef CONFIG_HW_WATCHDOG
- /* Enable watchdog before initializing the HW */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
- hw_watchdog_init();
-#endif
-
/* ensure all processors are not released prior Linux boot */
writeq(0, CPU_RELEASE_ADDR);
@@ -80,6 +73,13 @@ void board_init_f(ulong dummy)
hang();
}
+ /*
+ * Enable watchdog as early as possible before initializing other
+ * component.
+ */
+ if (CONFIG_IS_ENABLED(WDT))
+ initr_watchdog();
+
#ifdef CONFIG_DEBUG_UART
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
debug_uart_init();
DM WDT needs clock/reset; ordering after uclass_get_device(UCLASS_CLK)
matches spl_agilex.c and commit message rationale.
I agree, the commit message already describes this implementation -
"This requires clocks and reset to be valid for the L4 watchdog block,
and so it must run after the clock manager
(uclass_get_device(UCLASS_CLK)) succeeds."
Regards,
Alif
Best regards,
Tien Fong
