On 6/3/26 3:31 PM, Simona Toaca wrote:
[...]
I also do not see why I would check if the offset is a multiple of
the erase size, since the erase fails gracefully.
My understanding is, that the erase operation should erase the QB data
from the SPI NOR, not ignore failure and keep the data there ?
If there is data in SPI NOR it means that a previous write was successful,
thus the erase shouldn't fail (as the write method in qb save also uses erase).
It is possible to write to a non-erased SPI NOR, even at unaligned
address. It is not possible to erase at unaligned address.
It seems that on iMX95 B0, the DDR_DUMMY offset is 0x76400 (aligned to 1
kiB, which is too low):
Yes, this is indeed too low. We align our DDR_DUMMY offset to 0x1000 (4KiB) in
imx-mkimage, I see that here is not the case. At the same time, aligning
it everytime (even for eMMC/SD case) to 64KiB seems overkill.
Are you testing this patchset with upstream U-Boot mkimage ?
This makes the "qb save" work reliably even on SPI NOR, because the erase
block is aligned to 64 kiB instead of 1 kiB as it was before. Maybe we need
such an alignment change ?
My suggestion is that we align it with what happens in imx-mkimage
and make ddr_dummy take an additional argument specifying the alignment.
(and leave 4KiB default alignment in the dtsi, which should be fine if
SFDP is used).
If you're ok with this, I will start working on a patch.
This is fine by me, thank you.
