Hi Tien Fong,
On 3/6/2026 6:12 pm, Chee, Tien Fong wrote:
Hi Alif,
On 12/5/2026 2:49 pm, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]>
Relocate the dram_bank_mmu_setup() implementation from misc_arria10.c to
the common socfpga misc.c and update the function to correctly handle both
pre-relocation and post-relocation cases for DRAM cache enabling for
consistent MMU/dcache setup across Arria10 and CycloneV platforms.
These changes help to improve maintainability and consistency of DRAM
initialization as well as MMU configuration for Arria10 and CycloneV
platforms.
New Kconfig is introduced to enable this implementation only on the default
no Kconfig in this patch
Arria10 and CycloneV boards as this will increase the SPL size which
will exceed some Gen5 devices' SPL size limit.
Fixes: e26ecebc684b ("socfpga: arria10: Allow dcache_enable before relocation")
I think the commit message can be improved:
Share dram_bank_mmu_setup() between Gen5 and Arria10 in misc.c. Before
relocation, map OCRAM and DRAM write-through so SPL can run
sdram_init_ecc_bits() with dcache; after relocation, use default DRAM
cache attributes.
Fixes: 503eea451903 ("arm: cp15: update DACR value to activate access
control")
Link: e26ecebc684b ("socfpga: arria10: Allow dcache_enable before
relocation")
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
---
Changes in v3:
- Removed 'select SPL_CACHE if SPL' Kconfig guard from this patch and
applied this condition alongside SOCFPGA_ECC_SUPPORT on patch 3
Changes in v2:
- Shared dram_bank_mmu_setup() is set as optional via Kconfig and defaulted
on only for the reference Arria10/CycloneV boards to avoid SPL overflows
on size-limited Gen5 defconfigs.
arch/arm/mach-socfpga/misc.c | 31 ++++++++++++++++++++++++++++
arch/arm/mach-socfpga/misc_arria10.c | 26 -----------------------
2 files changed, 31 insertions(+), 26 deletions(-)
Best regards,
Tien Fong
Thank you for your suggestion. I will update the commit message based on
your input in v4.
Alif
