Hi Tom, On 5/21/2026 11:56 AM, Francesco Dolcini wrote: > On Wed, May 20, 2026 at 09:52:09PM +0000, Scholz, Kevin wrote: >> Francesco, >> >> My understanding is that the Aquila board was previously having >> intermittent boot failures, hence the comparison of the TI EVM >> register values vs. the Aquila board register values. My understanding >> is that since then, two unrelated issues were identified resulting in >> the observed behavior, and both have been resolved. > > My question has nothing to do with Aquila, I think I was not clear. > >> However in general, more than one IO setting can be adequate for a >> given design, and it is also acceptable to have different IO settings >> for different board designs and/or for different DDRSS on the same >> board. > > Again, nothing on my question relates to this. My question was > >>> specific configuration for AM69A SK board in which only dram3 has ODT >>> enabled, and dram, dram1 and dram2 not. Is the layout/schematics of >>> DRAM3 different from the others? Why? > > Why do dram3 is different from dram, dram1 and dram2 on AM69-SK ? Such a > difference implies that the layout is different, or something else. I am > interested in understand what's the reason. > > The question is because I want to understand better the TI design. > > On Thu, May 21, 2026 at 11:17:10AM +0530, Neha Malcom Francis wrote: >> On 2026-05-20 21:52:09+00:00, Scholz, Kevin wrote: >> Francesco, hope this justification on the IO settings are satisfactory. > > There is no answer to my question. > >> Tom, could we pick up this series in that case? > > From my point of view you can merge the series. It was like that even > before, I just abused this thread to gather more understanding on the > topic. I see no reason to hold this patch because of this. >
Could you pull in this series, Thanks > Francesco >
