Add initial set of clocks and resets for enabling U-Boot on ipq9650 based RDP platforms.
Changes in v2: - Fix SPDX license identifier to GPL-2.0-only (reported by Ferass) Signed-off-by: Badhrinath S <[email protected]> --- drivers/clk/qcom/Kconfig | 8 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-ipq9650.c | 95 ++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 drivers/clk/qcom/clock-ipq9650.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0a2ce55aaa2f..82c56cf605a8 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -47,6 +47,14 @@ config CLK_QCOM_IPQ9574 on the Snapdragon IPQ9574 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_IPQ9650 + bool "Qualcomm IPQ9650 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Qualcomm IPQ9650 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_MILOS bool "Qualcomm Milos GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b96d61b603e4..6cf069053743 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o +obj-$(CONFIG_CLK_QCOM_IPQ9650) += clock-ipq9650.o obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o diff --git a/drivers/clk/qcom/clock-ipq9650.c b/drivers/clk/qcom/clock-ipq9650.c new file mode 100644 index 000000000000..cdac71db4e1f --- /dev/null +++ b/drivers/clk/qcom/clock-ipq9650.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Clock drivers for Qualcomm ipq9650 + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,ipq9650-gcc.h> +#include <dt-bindings/reset/qcom,ipq9650-gcc.h> + +#include "clock-qcom.h" + +#define GCC_IM_SLEEP_CBCR 0x1834020u + +static ulong ipq9650_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_QUPV3_WRAP_SE6_CLK: + clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].reg, + 1, 2, 217, CFG_CLK_SRC_GPLL0, 8); + return rate; + case GCC_SDCC1_APPS_CLK: + clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].reg, + 5, 0, 0, CFG_CLK_SRC_GPLL2_MAIN, 16); + return rate; + } + return 0; +} + +static const struct gate_clk ipq9650_clks[] = { + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x3303c, BIT(0)), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x33004, BIT(1)), + GATE_CLK(GCC_QUPV3_WRAP_SE6_CLK, 0x04004, BIT(0)), +}; + +static int ipq9650_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= ARRAY_SIZE(ipq9650_clks) || !ipq9650_clks[clk->id].reg) + return -EINVAL; + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map ipq9650_gcc_resets[] = { + [GCC_SDCC_BCR] = { 0x33000 }, +}; + +static struct msm_clk_data ipq9650_gcc_data = { + .resets = ipq9650_gcc_resets, + .num_resets = ARRAY_SIZE(ipq9650_gcc_resets), + .clks = ipq9650_clks, + .num_clks = ARRAY_SIZE(ipq9650_clks), + + .enable = ipq9650_enable, + .set_rate = ipq9650_set_rate, +}; + +static const struct udevice_id gcc_ipq9650_of_match[] = { + { + .compatible = "qcom,ipq9650-gcc", + .data = (ulong)&ipq9650_gcc_data, + }, + { } +}; + +static int ipq9650_clk_probe(struct udevice *dev) +{ + /* Enable the sleep clock needed for the MMC block reset */ + writel(BIT(0), GCC_IM_SLEEP_CBCR); + + return 0; +} + +U_BOOT_DRIVER(gcc_ipq9650) = { + .name = "gcc_ipq9650", + .id = UCLASS_NOP, + .of_match = gcc_ipq9650_of_match, + .probe = ipq9650_clk_probe, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; -- 2.34.1
