Thanks and Best Regards Jerry Huang
> -----Original Message----- > From: Phillips Kim-R1AAHA > Sent: Thursday, November 03, 2011 4:37 AM > To: McClintock Matthew-B29882 > Cc: Huang Changming-R66093; Tabi Timur-B04825; [email protected]; > Phillips Kim-R1AAHA > Subject: Re: [U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz > oscillator support > > On Wed, 2 Nov 2011 09:52:17 -0500 > McClintock Matthew-B29882 <[email protected]> wrote: > > > On Wed, Nov 2, 2011 at 2:34 AM, Huang Changming-R66093 > > <[email protected]> wrote: > > >> > How can I deal with the new board and old board? > > >> > > >> Check the board revision at runtime. > > >> > > > Board Specification says, there is one EEPROM to contain all board > history, and I found it: > > > On I2C2 bus, there is one EEPROM BRD(0x50) from the schematics, but > the content of this EEPROM is 0xff. > > > That's to say, we can't check the board information from this > EEPROM. > > > From the code of mpc8360emds platform, there is not the interface > to check the board information. > > > > > > So, there is no way to check the board revision at runtime. > > Board revision information should be in BCSR12. I'm curious whether > yours contains a higher board revision level than mine: > > => md.b f8000000 e > f8000000: 04 04 00 c6 94 60 00 00 ac 2e 00 b8 10 3f .....`.......? > BCSR12->^^ My board BCSR info: => md.b f8000000 e f8000000: 0a 04 00 8f 94 60 00 00 ac 2e 00 b8 22 3f .....`......"? > because the sticker on the FPGA says "BCSR 2.1" vs. the "1.0" > encoding above. Best case explanation would be the h/w encoding is 0- > based and they don't bother to update the minor revision number... > > > Is your board special? Maybe the ones customers get go through the > > proper process to have EEPROM updated? Otherwise, you will probably > > need to create a new board type: > > > > $ make mpc8360emds_newmodifier > > wrt setting CONFIG_83XX_CLKIN, it's a little harder to do at runtime, > so we should do as Matt says instead of checking the board revision at > runtime - see e.g., the MPC8313ERDB_33 vs. > MPC8313ERDB_66 targets. The HRCW_LOW change should also be #ifdeffed. > > Some other comments on this patch, now that I've taken a closer look: > > 1. it should be two patches - one for the CLKIN change, the other for > the dynamic remapping change. > > 2. update doc/README.mpc8360emds for 33 vs. 66 a la > doc/README.mpc8313erdb, and also for the remapping change, each update > in its corresponding patch. Might want to mention any dip switch > setting changes and the physical location of the oscillator so the user > is sure which one to use - CLKIN is the one closest to the JTAG > connector, right? Yes, it is U41. > 3. no need to sync after write_bat(); write_bat() does this already. > > 4. no need to clear BATs before writing them either. > > 5. I can't comprehend the comment "re-setup PCI MEM space used BAT5 > after relocated to DDR" - do you mean something like "reuse BAT5 for > PCI MEM space after relocation to RAM"? Yes, I will change the comment. > 6. re-post patches to this thread - see the 3rd bullet in: > > http://www.denx.de/wiki/view/U- > Boot/Patches#Sending_updated_patch_versions > > Thanks, > > Kim _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
