From: Dinesh Maniyam <[email protected]> Replace the early legacy CONFIG_HW_WATCHDOG path (L4WD0 reset toggle plus hw_watchdog_init()) with DM watchdog initialization via initr_watchdog() when CONFIG_WDT is enabled.
Call initr_watchdog() after the clock drivers probe and before DDR and other later board_init_f() steps so the watchdog can obtain its clock rate, while still running from on-chip RAM in SPL. Signed-off-by: Dinesh Maniyam <[email protected]> --- Changes in v2: - Rename subject to arm: socfpga: spl_n5x: ... - Expand commit message for HW_WATCHDOG -> DM WDT switch - Drop unused smmu_s10.h include - Comment wording cleanups History: -------- [v1] https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/ arch/arm/mach-socfpga/spl_n5x.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index a49be837921..93424c2513c 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -17,7 +17,7 @@ #include <image.h> #include <init.h> #include <spl.h> -#include <watchdog.h> +#include <wdt.h> void board_init_f(ulong dummy) { @@ -34,13 +34,6 @@ void board_init_f(ulong dummy) writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); -#ifdef CONFIG_HW_WATCHDOG - /* Enable watchdog before initializing the HW */ - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); - hw_watchdog_init(); -#endif - /* ensure all processors are not released prior Linux boot */ writeq(0, CPU_RELEASE_ADDR); @@ -66,6 +59,15 @@ void board_init_f(ulong dummy) hang(); } + /* + * Enable watchdog as early as possible before initializing other + * components. Watchdog needs to be enabled after the clock driver + * because it retrieves the watchdog clock frequency from the clock + * driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + print_reset_info(); cm_print_clock_quick_summary(); -- 2.43.7
