Convert the USB3 and UFS PHY reference clocks in the sa8775p gate clock table from GATE_CLK() to GATE_CLK_POLLED(), so their enable status is polled against the per-clock CBCR register instead of assuming the enable write completed immediately.
Signed-off-by: Balaji Selvanathan <[email protected]> --- drivers/clk/qcom/clock-sa8775p.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index 7eec4aeae48..c36b480b300 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -118,14 +118,14 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) } static const struct gate_clk sa8775p_clks[] = { - GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1), - GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1), - GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1), - GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1), - GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, 1), + GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, BIT(0), 0x1b088), + GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, BIT(0), 0x1b018), + GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, BIT(0), 0x1b084), + GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, BIT(0), 0x1b020), + GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, BIT(0), 0x1b024), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, BIT(0), 0x1b05c), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, BIT(0), 0x1b060), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, BIT(0), 0x1b064), /* QUP Wrapper 0 clocks */ GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), @@ -157,18 +157,18 @@ static const struct gate_clk sa8775p_clks[] = { GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT), /* UFS PHY clocks */ - GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1), - GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1), - GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1), - GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1), - GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1), - GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1), - GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1), - GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1), - GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1), + GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0), 0x83018), + GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, BIT(0), 0x830d4), + GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x83020, BIT(0), 0x83020), + GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0), 0x83064), + GATE_CLK_POLLED(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, BIT(0), 0x83024), + GATE_CLK_POLLED(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, BIT(0), 0x83028), + GATE_CLK_POLLED(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, BIT(0), 0x830c0), + GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, BIT(0), 0x830a4), + GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, BIT(0), 0x8306c), /* EDP reference clock (used by UFS PHY) */ - GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1), + GATE_CLK_POLLED(GCC_EDP_REF_CLKREF_EN, 0x97448, BIT(0), 0x97448), }; static int sa8775p_enable(struct clk *clk) -- 2.34.1
