On Thu, Jul 23, 2026 at 12:09:46PM +0530, Balaji Selvanathan via U-Boot wrote: > Convert the USB3 and UFS PHY reference clocks in the sa8775p gate > clock table from GATE_CLK() to GATE_CLK_POLLED(), so their enable > status is polled against the per-clock CBCR register instead of > assuming the enable write completed immediately. > > Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Varadarajan Narayanan <[email protected]>
