[PATCH v2 3/5] clk: rockchip: pll: fix RK3588 frac PLL result for k=-32768

[Alexey Charkov]

Current code needlessly sets the k value to 0 when it is calculated as
-32768, which is a valid value for the RK3588 frac PLL. This results in
the PLL output frequency being higher than requested when the requested
frequency is exactly halfway between two integer-multiplier PLL output
frequencies.

Negative values of k cannot be greater than 32768 in magnitude either,
because that case has been handled just above the enclosing if statement,
so the check for k > 32767 is redundant.

Fixes: 6bfb37e70209 ("clk: rockchip: rk3588: fix up the frac pll calculation")
Signed-off-by: Alexey Charkov <alch...@flipper.net>
---
 drivers/clk/rockchip/clk_pll.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 69d2d182dcb5..6cef5a36ccfe 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -182,10 +182,7 @@ rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, 
u64 fvco)
                 * Round up to avoid overshooting requested rate for negative k
                 */
                k = DIV64_U64_ROUND_UP(ffrac * 65536, fref);
-               if (k > 32767)
-                       k = 0;
-               else
-                       k = ~k + 1;
+               k = ~k + 1;
        }
        return k;
 }

-- 
2.54.0