Hi Quentin, On Fri, Aug 7, 2026 at 1:10 PM Quentin Schulz <[email protected]> wrote: > > Hi Alexey, > > On 7/29/26 4:22 PM, Alexey Charkov wrote: > > Hi Quentin, > > > > On Thu, Jul 23, 2026 at 7:04 PM Alexey Charkov <[email protected]> wrote: > >> > >> Current fractional PLL code for RK3588 (also applies to RK3576) has two > >> issues causing it to overshoot the requested frequency for some negative > >> values of the fractional coefficient: one due to rounding, the other due > >> to treating -32768 as an invalid value where it is actually valid. It > >> also overflows the calculation of the fractional PLL rate when reading > >> it back, causing the function to return wrong PLL frequencies for non- > >> trivial values of the fractional coefficient. > >> > >> Fix all three, and also use native signed integer arithmetics to avoid > >> manual bitwise operations on the unsigned representation of the fractional > >> coefficient, which simplifies the code and makes it easier to read. > >> > >> Signed-off-by: Alexey Charkov <[email protected]> > >> --- > >> Changes in v2: > >> - Pass a pointer to the full table entry to rockchip_rk3588_pll_k_get() > >> to make it the single source of truth for both m and k in the fractional > >> PLL auto-calculation path (thanks Quentin) > >> - Do the unsigned->signed conversion in a single patch instead of > >> scattering it across several smaller changes (thanks Quentin) > >> - Use s16 to hold the value of k in the rate table, in line with what > >> the hardware uses and also with my similar change submitted to Linux > >> - Add a comment in code with the actual clock rate formulas for easier > >> future reference > >> - Link to v1: > >> https://patch.msgid.link/[email protected] > >> > >> To: [email protected] > >> To: Elaine Zhang <[email protected]> > >> To: Jagan Teki <[email protected]> > >> Cc: Lukasz Majewski <[email protected]> > >> Cc: Simon Glass <[email protected]> > >> Cc: Philipp Tomsich <[email protected]> > >> Cc: Kever Yang <[email protected]> > >> Cc: Tom Rini <[email protected]> > >> Cc: Alexey Charkov <[email protected]> > >> Cc: Quentin Schulz <[email protected]> > >> Cc: Ilias Apalodimas <[email protected]> > >> Cc: Jonas Karlman <[email protected]> > >> Cc: Finley Xiao <[email protected]> > >> > >> --- > >> Alexey Charkov (5): > >> clk: rockchip: pll: drop misleading fout in > >> rockchip_rk3588_pll_k_get() > >> clk: rockchip: pll: fix rounding of negative k in RK3588 frac PLL > >> clk: rockchip: pll: fix RK3588 frac PLL result for k=-32768 > >> clk: rockchip: pll: let rockchip_rk3588_pll_k_get update m directly > >> clk: rockchip: pll: fix overflow and drop manual two's complement > >> on RK3588/RK3576 > >> > >> arch/arm/include/asm/arch-rockchip/clock.h | 8 +-- > >> drivers/clk/rockchip/clk_pll.c | 86 > >> +++++++++++++----------------- > >> 2 files changed, 41 insertions(+), 53 deletions(-) > > > > I see that Heiko applied the Linux version of related patches [1]. Is > > this one good to go, or would you like any changes first? > > > > I'll be waiting on > https://lore.kernel.org/u-boot/[email protected]/ > to get merged first and then I'll pick this up. Don't hesitate to ping > me as soon as it gets merged so I don't forget. > > Thanks for working this out with the Linux kernel and looking at fixing > U-Boot's div64/math64 :)
Makes sense, thank you! Simon asked there for a test case to be added to avoid future regressions, so I might need to spin another version. Will keep you posted. P.S. Yaay, lore is back to life! That's a relief! Best regards, Alexey
