Hi Tom, The following changes since commit b635d43bca429500cb8ef20aa151cb5773b9a8a5:
Merge patch series "fs/squashfs: fix symlink load failure on large images" (2026-07-25 07:55:35 -0600) are available in the Git repository at: [email protected]:u-boot/custodians/u-boot-riscv.git main for you to fetch changes up to c201051a9cd3a358cb67cbba9b1c5fa717cf1c40: serial: sifive: remove busy-loops from getc and putc ops (2026-07-26 21:04:42 -0700) CI result shows no issue: https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv/-/pipelines/740 ---------------------------------------------------------------- - some fixes - Add Yao Zi as a reviewer ---------------------------------------------------------------- Charles Perry (1): riscv: remove log_debug() in enable_caches() Francois Berder (1): rng: jh7110: Fix invalid usage of dev_read_addr Hal Feng (2): configs: visionfive2: Add VisionFive 2 Lite eMMC DT to OF_LIST board: starfive: visionfive2: Support VisionFive 2 Lite eMMC Hiago De Franco (2): doc: sophgo: licheerv_nano: fix incorrect step numbering riscv: dts: cv18xx: fix spi node name Michal Simek (3): riscv: Skip riscv_cpu_setup() when CPU driver is disabled riscv: Make RISCV_ACLINT visible riscv: Exclude ACLINT for TARGET_XILINX_MBV Naveen Kumar Chaudhary (1): serial: sifive: remove busy-loops from getc and putc ops Yao Zi (1): MAINTAINERS: riscv: Add myself as a reviewer MAINTAINERS | 1 + arch/riscv/Kconfig | 4 ++-- arch/riscv/cpu/cpu.c | 3 +++ arch/riscv/dts/cv18xx.dtsi | 2 +- arch/riscv/lib/cache.c | 2 -- board/starfive/visionfive2/spl.c | 7 ++++++- board/starfive/visionfive2/starfive_visionfive2.c | 6 +++++- configs/starfive_visionfive2_defconfig | 2 +- configs/xilinx_mbv32_defconfig | 2 ++ doc/board/sophgo/licheerv_nano.rst | 4 ++-- drivers/rng/jh7110_rng.c | 4 ++-- drivers/serial/serial_sifive.c | 11 ++--------- 12 files changed, 27 insertions(+), 21 deletions(-) Best regards, Leo
