The dsmpd flag determines when a rk3036_pll fracpll should enable or bypass use of fractal mode.
Change to always write the value of the dsmpd flag to reg to allow fractal re-configuration and closer match how Linux behaves. Signed-off-by: Jonas Karlman <[email protected]> --- drivers/clk/rockchip/clk_pll.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 4fe67c889376..a135fad3de0c 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -326,13 +326,12 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, rate->fbdiv); rk_clrsetreg(base + pll->con_offset + 0x4, (RK3036_PLLCON1_POSTDIV2_MASK | - RK3036_PLLCON1_REFDIV_MASK), + RK3036_PLLCON1_REFDIV_MASK | + RK3036_PLLCON1_DSMPD_MASK), (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | - rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); + rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT | + rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT)); if (!rate->dsmpd) { - rk_clrsetreg(base + pll->con_offset + 0x4, - RK3036_PLLCON1_DSMPD_MASK, - rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); writel((readl(base + pll->con_offset + 0x8) & (~RK3036_PLLCON2_FRAC_MASK)) | (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), -- 2.54.0
