The possible frac_rate part of rk3036_pll plls is divided two times by postdiv1 instead of both postdiv1 and postdiv2 as the integer part. Fix this by using postdiv2 in the second do_div() call.
Signed-off-by: Jonas Karlman <[email protected]> --- drivers/clk/rockchip/clk_pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 9dec40b1fe83..4fe67c889376 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -405,7 +405,7 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, do_div(frac_rate, refdiv); frac_rate >>= 24; do_div(frac_rate, postdiv1); - do_div(frac_rate, postdiv1); + do_div(frac_rate, postdiv2); rate += frac_rate; } return rate; -- 2.54.0
