Add the required include for the MT6366 PMIC and add the pwrap node used to communicate with it.
Now that we have the correct regulator providers from the PMIC, we can replace the fake regulators that were being used to make the eMMC work. Signed-off-by: David Lechner <[email protected]> --- arch/arm/dts/mt8366-genio-360-evk-common.dtsi | 23 +++-------------------- arch/arm/dts/mt8366.dtsi | 12 ++++++++++++ 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/arch/arm/dts/mt8366-genio-360-evk-common.dtsi b/arch/arm/dts/mt8366-genio-360-evk-common.dtsi index 13055e4740c..8157d8f8da1 100644 --- a/arch/arm/dts/mt8366-genio-360-evk-common.dtsi +++ b/arch/arm/dts/mt8366-genio-360-evk-common.dtsi @@ -5,6 +5,7 @@ */ #include "mt8366.dtsi" +#include "mt6366.dtsi" / { memory@40000000 { @@ -59,24 +60,6 @@ stdout-path = &uart0; }; - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - usb_p0_vbus: regulator-usb-p0 { compatible = "regulator-fixed"; regulator-name = "usb_p0_vbus"; @@ -376,8 +359,8 @@ mmc-hs400-1_8v; hs400-ds-delay = <0x10100>; cap-mmc-hw-reset; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; + vmmc-supply = <&mt6366_vemc_reg>; + vqmmc-supply = <&mt6366_vio18_reg>; non-removable; status = "okay"; }; diff --git a/arch/arm/dts/mt8366.dtsi b/arch/arm/dts/mt8366.dtsi index 263b0149a85..9fc4c9cfcaf 100644 --- a/arch/arm/dts/mt8366.dtsi +++ b/arch/arm/dts/mt8366.dtsi @@ -229,6 +229,18 @@ #clock-cells = <1>; }; + pwrap: pwrap@10026000 { + compatible = "mediatek,mt8366-pwrap", "mediatek,mt8195-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REG_PMIC_AP>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REG_PMIC_TMR>, + <&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>, + <&topckgen_clk CLK_TOP_OSC_D10>; + clock-names = "spi", "wrap", "sys", "tmr"; + }; + gce_clk: clock-controller@10228000 { compatible = "mediatek,mt8366-gce"; reg = <0 0x10228000 0 0x1000>; -- 2.43.0
