From: Christian Marangi <[email protected]> Add support for Airoha AN7583 SoC clock that implement more base values for clocks compared to AN7581.
Signed-off-by: Christian Marangi <[email protected]> --- drivers/clk/airoha/clk-airoha.c | 158 ++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/drivers/clk/airoha/clk-airoha.c b/drivers/clk/airoha/clk-airoha.c index 89a8b4cb1cf..23cb04aa5ef 100644 --- a/drivers/clk/airoha/clk-airoha.c +++ b/drivers/clk/airoha/clk-airoha.c @@ -36,6 +36,7 @@ #define EN7523_MAX_CLKS 8 #define EN7581_MAX_CLKS 9 +#define EN7583_MAX_CLKS 11 struct airoha_clk_desc { int id; @@ -78,6 +79,14 @@ static const u32 bus7581_base[] = { 600000000, 540000000 }; static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; static const u32 crypto_base[] = { 540000000, 480000000 }; static const u32 emmc7581_base[] = { 200000000, 150000000 }; +/* AN7583 */ +static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 }; +static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 }; +static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 }; +static const u32 spi7583_base[] = { 400000000, 12500000 }; +static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 }; +static const u32 crypto7583_base[] = { 540672000, 400000000 }; +static const u32 emmc7583_base[] = { 150000000, 200000000 }; static const struct airoha_clk_desc en7523_base_clks[EN7523_MAX_CLKS] = { [EN7523_CLK_GSW] = { @@ -293,6 +302,147 @@ static const struct airoha_clk_desc en7581_base_clks[EN7581_MAX_CLKS] = { } }; +static const struct airoha_clk_desc an7583_base_clks[EN7583_MAX_CLKS] = { + [EN7523_CLK_GSW] = { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = gsw7583_base, + .n_base_values = ARRAY_SIZE(gsw7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, + [EN7523_CLK_EMI] = { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = emi7583_base, + .n_base_values = ARRAY_SIZE(emi7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, + [EN7523_CLK_BUS] = { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = bus7583_base, + .n_base_values = ARRAY_SIZE(bus7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, + [EN7523_CLK_SLIC] = { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 1, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, + [EN7523_CLK_SPI] = { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = spi7583_base, + .n_base_values = ARRAY_SIZE(spi7583_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, + [EN7523_CLK_NPU] = { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 9, + .base_values = npu7583_base, + .n_base_values = ARRAY_SIZE(npu7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, + [EN7523_CLK_CRYPTO] = { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC2, + .base_bits = 1, + .base_shift = 0, + .base_values = crypto7583_base, + .n_base_values = ARRAY_SIZE(crypto7583_base), + }, + [EN7581_CLK_EMMC] = { + .id = EN7581_CLK_EMMC, + .name = "emmc", + + .base_reg = REG_CRYPTO_CLKSRC2, + .base_bits = 1, + .base_shift = 13, + .base_values = emmc7583_base, + .n_base_values = ARRAY_SIZE(emmc7583_base), + }, + [AN7583_CLK_MDIO0] = { + .id = AN7583_CLK_MDIO0, + .name = "mdio0", + + .base_reg = REG_CRYPTO_CLKSRC2, + + .base_value = 25000000, + + .div_bits = 4, + .div_shift = 15, + .div_step = 1, + .div_offset = 1, + }, + [AN7583_CLK_MDIO1] = { + .id = AN7583_CLK_MDIO1, + .name = "mdio1", + + .base_reg = REG_CRYPTO_CLKSRC2, + + .base_value = 25000000, + + .div_bits = 4, + .div_shift = 19, + .div_step = 1, + .div_offset = 1, + } +}; + static u32 airoha_clk_get_base_rate(const struct airoha_clk_desc *desc, u32 val) { if (!desc->base_bits) @@ -542,6 +692,11 @@ static const struct airoha_clk_soc_data en7581_data = { .descs = en7581_base_clks, }; +static const struct airoha_clk_soc_data an7583_data = { + .num_clocks = ARRAY_SIZE(an7583_base_clks), + .descs = an7583_base_clks, +}; + static const struct udevice_id airoha_clk_ids[] = { { .compatible = "airoha,en7523-scu", .data = (ulong)&en7523_data, @@ -549,6 +704,9 @@ static const struct udevice_id airoha_clk_ids[] = { { .compatible = "airoha,en7581-scu", .data = (ulong)&en7581_data, }, + { .compatible = "airoha,an7583-scu", + .data = (ulong)&an7583_data, + }, { } }; -- 2.53.0
