From: Christian Marangi <[email protected]> Adapt the Airoha reset driver to support Airoha AN7583 node structure. In AN7583 the register is exposed by the parent syscon hence a different logic needs to be applied. Also the reset line differ from AN7581 hence a dedicated table is needed.
Signed-off-by: Christian Marangi <[email protected]> --- drivers/reset/reset-airoha.c | 60 ++++++++++++++++++ .../dt-bindings/reset/airoha,an7583-reset.h | 62 +++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h diff --git a/drivers/reset/reset-airoha.c b/drivers/reset/reset-airoha.c index ef8c47a067b..071f29b6f22 100644 --- a/drivers/reset/reset-airoha.c +++ b/drivers/reset/reset-airoha.c @@ -15,6 +15,7 @@ #include <dt-bindings/reset/airoha,en7523-reset.h> #include <dt-bindings/reset/airoha,en7581-reset.h> +#include <dt-bindings/reset/airoha,an7583-reset.h> #define RST_NR_PER_BANK 32 @@ -138,6 +139,60 @@ static const u16 en7581_rst_map[] = { [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, }; +static const u16 an7583_rst_map[] = { + /* RST_CTRL2 */ + [AN7583_XPON_PHY_RST] = 0, + [AN7583_GPON_OLT_RST] = 1, + [AN7583_CPU_TIMER2_RST] = 2, + [AN7583_HSUART_RST] = 3, + [AN7583_UART4_RST] = 4, + [AN7583_UART5_RST] = 5, + [AN7583_I2C2_RST] = 6, + [AN7583_XSI_MAC_RST] = 7, + [AN7583_XSI_PHY_RST] = 8, + [AN7583_NPU_RST] = 9, + [AN7583_TRNG_MSTART_RST] = 12, + [AN7583_DUAL_HSI0_RST] = 13, + [AN7583_DUAL_HSI1_RST] = 14, + [AN7583_DUAL_HSI0_MAC_RST] = 16, + [AN7583_DUAL_HSI1_MAC_RST] = 17, + [AN7583_XPON_XFI_RST] = 18, + [AN7583_WDMA_RST] = 19, + [AN7583_WOE0_RST] = 20, + [AN7583_HSDMA_RST] = 22, + [AN7583_TDMA_RST] = 24, + [AN7583_EMMC_RST] = 25, + [AN7583_SOE_RST] = 26, + [AN7583_XFP_MAC_RST] = 28, + [AN7583_MDIO0] = 30, + [AN7583_MDIO1] = 31, + /* RST_CTRL1 */ + [AN7583_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, + [AN7583_FE_PDMA_RST] = RST_NR_PER_BANK + 1, + [AN7583_FE_QDMA_RST] = RST_NR_PER_BANK + 2, + [AN7583_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, + [AN7583_CRYPTO_RST] = RST_NR_PER_BANK + 6, + [AN7583_TIMER_RST] = RST_NR_PER_BANK + 8, + [AN7583_PCM1_RST] = RST_NR_PER_BANK + 11, + [AN7583_UART_RST] = RST_NR_PER_BANK + 12, + [AN7583_GPIO_RST] = RST_NR_PER_BANK + 13, + [AN7583_GDMA_RST] = RST_NR_PER_BANK + 14, + [AN7583_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, + [AN7583_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, + [AN7583_SFC_RST] = RST_NR_PER_BANK + 18, + [AN7583_UART2_RST] = RST_NR_PER_BANK + 19, + [AN7583_GDMP_RST] = RST_NR_PER_BANK + 20, + [AN7583_FE_RST] = RST_NR_PER_BANK + 21, + [AN7583_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, + [AN7583_GSW_RST] = RST_NR_PER_BANK + 23, + [AN7583_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, + [AN7583_PCIE0_RST] = RST_NR_PER_BANK + 26, + [AN7583_PCIE1_RST] = RST_NR_PER_BANK + 27, + [AN7583_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, + [AN7583_PCIE_HB_RST] = RST_NR_PER_BANK + 29, + [AN7583_XPON_MAC_RST] = RST_NR_PER_BANK + 31, +}; + static int airoha_reset_update(struct airoha_reset_priv *priv, unsigned long id, bool assert) { @@ -227,6 +282,11 @@ static int airoha_reset_probe(struct udevice *dev) return reset_init(dev, en7581_rst_map, ARRAY_SIZE(en7581_rst_map)); + if (ofnode_device_is_compatible(dev_ofnode(dev), + "airoha,an7583-scu")) + return reset_init(dev, an7583_rst_map, + ARRAY_SIZE(an7583_rst_map)); + return -ENODEV; } diff --git a/include/dt-bindings/reset/airoha,an7583-reset.h b/include/dt-bindings/reset/airoha,an7583-reset.h new file mode 100644 index 00000000000..be80d0e0bf5 --- /dev/null +++ b/include/dt-bindings/reset/airoha,an7583-reset.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi <[email protected]> + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ + +/* RST_CTRL2 */ +#define AN7583_XPON_PHY_RST 0 +#define AN7583_GPON_OLT_RST 1 +#define AN7583_CPU_TIMER2_RST 2 +#define AN7583_HSUART_RST 3 +#define AN7583_UART4_RST 4 +#define AN7583_UART5_RST 5 +#define AN7583_I2C2_RST 6 +#define AN7583_XSI_MAC_RST 7 +#define AN7583_XSI_PHY_RST 8 +#define AN7583_NPU_RST 9 +#define AN7583_TRNG_MSTART_RST 10 +#define AN7583_DUAL_HSI0_RST 11 +#define AN7583_DUAL_HSI1_RST 12 +#define AN7583_DUAL_HSI0_MAC_RST 13 +#define AN7583_DUAL_HSI1_MAC_RST 14 +#define AN7583_XPON_XFI_RST 15 +#define AN7583_WDMA_RST 16 +#define AN7583_WOE0_RST 17 +#define AN7583_HSDMA_RST 18 +#define AN7583_TDMA_RST 19 +#define AN7583_EMMC_RST 20 +#define AN7583_SOE_RST 21 +#define AN7583_XFP_MAC_RST 22 +#define AN7583_MDIO0 23 +#define AN7583_MDIO1 24 +/* RST_CTRL1 */ +#define AN7583_PCM1_ZSI_ISI_RST 25 +#define AN7583_FE_PDMA_RST 26 +#define AN7583_FE_QDMA_RST 27 +#define AN7583_PCM_SPIWP_RST 28 +#define AN7583_CRYPTO_RST 29 +#define AN7583_TIMER_RST 30 +#define AN7583_PCM1_RST 31 +#define AN7583_UART_RST 32 +#define AN7583_GPIO_RST 33 +#define AN7583_GDMA_RST 34 +#define AN7583_I2C_MASTER_RST 35 +#define AN7583_PCM2_ZSI_ISI_RST 36 +#define AN7583_SFC_RST 37 +#define AN7583_UART2_RST 38 +#define AN7583_GDMP_RST 39 +#define AN7583_FE_RST 40 +#define AN7583_USB_HOST_P0_RST 41 +#define AN7583_GSW_RST 42 +#define AN7583_SFC2_PCM_RST 43 +#define AN7583_PCIE0_RST 44 +#define AN7583_PCIE1_RST 45 +#define AN7583_CPU_TIMER_RST 46 +#define AN7583_PCIE_HB_RST 47 +#define AN7583_XPON_MAC_RST 48 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */ -- 2.53.0
