Most of the simple display pipeline components share the same probe and enable sequence: remap the register window and enable a bulk of clocks. Add the mtk_disp_comp helpers holding this boilerplate so each component driver only has to provide its own component-specific programming.
Signed-off-by: Julien Stephan <[email protected]> --- drivers/video/mediatek/mtk_disp_comp.c | 90 ++++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_disp_comp.h | 34 +++++++++++++ 2 files changed, 124 insertions(+) diff --git a/drivers/video/mediatek/mtk_disp_comp.c b/drivers/video/mediatek/mtk_disp_comp.c new file mode 100644 index 00000000000..d41440f06ab --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_comp.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MediaTek display pipeline component helpers + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan <[email protected]> + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <mtk_smi.h> + +#include "mtk_disp_comp.h" + +void mtk_disp_comp_write(struct udevice *dev, u32 offset, u32 val) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + + writel(val, priv->base + offset); +} + +void mtk_disp_comp_update(struct udevice *dev, u32 offset, u32 val, u32 mask) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + void __iomem *reg = priv->base + offset; + u32 tmp; + + tmp = readl(reg); + tmp = (tmp & ~mask) | (val & mask); + writel(tmp, reg); +} + +int mtk_disp_comp_enable(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + /* ungate the feeding SMI larb first, if any */ + if (priv->larb) { + ret = mtk_smi_larb_enable(priv->larb); + if (ret) + return ret; + } + + ret = clk_enable_bulk(&priv->clk_bulk); + if (ret) { + dev_err(dev, "failed to enable clocks: %d\n", ret); + if (priv->larb) + mtk_smi_larb_disable(priv->larb); + return ret; + } + + return 0; +} + +int mtk_disp_comp_disable(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_disable_bulk(&priv->clk_bulk); + if (ret) + dev_err(dev, "failed to disable clocks: %d\n", ret); + + if (priv->larb) + mtk_smi_larb_disable(priv->larb); + + return ret; +} + +int mtk_disp_comp_probe(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_bulk(dev, &priv->clk_bulk); + if (ret) { + dev_err(dev, "failed to get clocks: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/drivers/video/mediatek/mtk_disp_comp.h b/drivers/video/mediatek/mtk_disp_comp.h new file mode 100644 index 00000000000..f538129b7cb --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_comp.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MediaTek display pipeline component helpers + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan <[email protected]> + */ + +#ifndef _MTK_DISP_COMP_H +#define _MTK_DISP_COMP_H + +#include <clk.h> + +struct udevice; + +/* + * Common state shared by all the simple display pipeline components: + * a register window and a bulk of clocks. @larb is an optional SMI larb + * device (UCLASS_MEMORY) enabled and disabled together with the component + * (used by the RDMAs, which are the DMA masters of this pipeline). + */ +struct mtk_disp_comp_priv { + void __iomem *base; + struct clk_bulk clk_bulk; + struct udevice *larb; +}; + +int mtk_disp_comp_probe(struct udevice *dev); +int mtk_disp_comp_enable(struct udevice *dev); +int mtk_disp_comp_disable(struct udevice *dev); +void mtk_disp_comp_write(struct udevice *dev, u32 offset, u32 val); +void mtk_disp_comp_update(struct udevice *dev, u32 offset, u32 val, u32 mask); + +#endif /* _MTK_DISP_COMP_H */ -- 2.55.0
