On 8/28/2026 7:27 PM, Richard Genoud (TI) wrote:
> From: Abhash Kumar Jha <[email protected]>
>
> The GTC counter values are restored in the resume sequence by TIFS as
> part of the core_resume API. Enable GTC counter after it is restored.
>
> Also add a check to make sure that rproc_load only enables the GTC counter
> in the case of a cold boot.
>
> Signed-off-by: Abhash Kumar Jha <[email protected]>
> Co-developed-by: Richard Genoud (TI) <[email protected]>
> Signed-off-by: Richard Genoud (TI) <[email protected]>
> ---
> arch/arm/mach-k3/r5/lpm-common.c | 11 +++++++++++
> drivers/remoteproc/ti_k3_arm64_rproc.c | 10 ++++++++--
> 2 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-k3/r5/lpm-common.c
> b/arch/arm/mach-k3/r5/lpm-common.c
> index ab39ea0cd67d..4f515b51fd40 100644
> --- a/arch/arm/mach-k3/r5/lpm-common.c
> +++ b/arch/arm/mach-k3/r5/lpm-common.c
> @@ -311,6 +311,7 @@ static void resume_rproc_f(void)
> {
> struct power_domain rproc_pwrdmn;
> struct udevice *dev;
> + void *gtc_base;
> int ret;
>
> ret = uclass_get_device_by_seq(UCLASS_REMOTEPROC, 1, &dev);
> @@ -321,6 +322,16 @@ static void resume_rproc_f(void)
> if (ret)
> panic("power_domain_get_rproc() failed: %d\n", ret);
>
> + gtc_base = dev_read_addr_ptr(dev);
> + if (!gtc_base)
> + panic("Get GTC address failed\n");
> +
> +#define GTC_CNTCR_REG 0x0
> +#define GTC_CNTR_EN 0x3
> +
> + /* GTC counter values have been restored by TIFS, so enable the counter
> */
> + writel(GTC_CNTR_EN, gtc_base + GTC_CNTCR_REG);
> +
> ret = power_domain_on(&rproc_pwrdmn);
> if (ret)
> panic("power_domain_on failed: %d\n", ret);
> diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c
> b/drivers/remoteproc/ti_k3_arm64_rproc.c
> index 403c6bed2e8c..9b8a6b7dc53a 100644
> --- a/drivers/remoteproc/ti_k3_arm64_rproc.c
> +++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
> @@ -17,6 +17,7 @@
> #include <dm/device_compat.h>
> #include <linux/err.h>
> #include <linux/soc/ti/ti_sci_protocol.h>
> +#include <mach/hardware.h>
> #include "ti_sci_proc.h"
>
> #define INVALID_ID 0xff
> @@ -78,8 +79,13 @@ static int k3_arm64_load(struct udevice *dev, ulong addr,
> ulong size)
> /* Store the clock frequency down for GTC users to pick up */
> writel((u32)gtc_rate, rproc->gtc_base + GTC_CNTFID0_REG);
>
> - /* Enable the timer before starting remote core */
> - writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG);
> + if (!j7xx_board_is_resuming()) {
> + /*
> + * In case of a fresh boot, enable the timer before
> + * starting the remote core.
> + */
> + writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG);
> + }
>
> /*
> * Setting the right clock frequency would have taken care by
Reviewed-by: Udit Kumar <[email protected]>
