Add the 'serdes1' hwconfig option to README.fsl-hwconfig and a short note to the Layerscape README.soc.
Signed-off-by: Vincent Jardin <[email protected]> --- (no changes since v1) .../cpu/armv8/fsl-layerscape/doc/README.soc | 10 ++++++++ doc/README.fsl-hwconfig | 25 +++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index f2efd4cc1d7..a6f729059a1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -332,6 +332,16 @@ LX2160A SoC has 2 more similar SoC personalities a) Eight 64-bit ARM v8 Cortex-A72 CPUs +SerDes 1 runtime lane grouping + The SerDes 1 protocol selected by the RCW (SRDS_PRTCL_S1) is latched + at reset and cannot be changed afterwards. On the LX2160A boards under + board/nxp/lx2160a/, U-Boot can nevertheless re-group the eight SerDes 1 + lanes before the management complex starts: 2x 100GE can become + 1x 100GE + 4x 25G, 2x 40GE, 1x 40GE + 4x 10G or 1x 100GE + 4x 10G. + See the 'lx2160_sd1' and 'lx2160_serdes' commands and the 'serdes1' + option in doc/README.fsl-hwconfig. + + LS1028A -------- The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig index e752505da49..605a5fd0d77 100644 --- a/doc/README.fsl-hwconfig +++ b/doc/README.fsl-hwconfig @@ -44,3 +44,28 @@ usb usb1:dr_mode=host;usb2:dr_mode=peripheral' usb1:dr_mode=host,phy_type=utmi;usb2:dr_mode=host' + +serdes1 + Specific to the LX2160A boards under board/nxp/lx2160a/. + + This option re-groups the eight lanes of SerDes 1 at boot, before + the DPAA2 management complex latches the protocol converters. The + RCW-selected SerDes 1 protocol (SRDS_PRTCL_S1) is latched at reset + and cannot be changed; these modes change what the lanes carry + while keeping that protocol number. The same modes are available + at the prompt through the 'lx2160_sd1' command, and 'lx2160_serdes + status' shows the resulting lane grouping. + + 'serdes1:100g4x25g' + 2x 100GE -> 1x 100GE + 4x 25G + + 'serdes1:2x40g' + 2x 100GE -> 2x 40GE + + 'serdes1:40g4x10g' + 1x 40GE + 4x 10G (converts to 2x 40GE first if needed) + + 'serdes1:100g4x10g' + 1x 100GE + 4x 10G + + Only one of them applies; '100g4x25g' wins if several are given. -- 2.43.0
