Replace the open-coded struct mtk_clk_tree definitions of the blocks that only provide gates with the MTK_GATE_CLK_TREE() helper.
The helper also sets .gates_offs to the ID of the first gate of the block. All the converted blocks start at ID 0, so this is a no-op. No functional change. Signed-off-by: Julien Stephan <[email protected]> --- drivers/clk/mediatek/clk-mt8183.c | 7 +---- drivers/clk/mediatek/clk-mt8188.c | 63 ++++++-------------------------------- drivers/clk/mediatek/clk-mt8195.c | 7 +---- drivers/clk/mediatek/clk-mt8365.c | 7 +---- drivers/clk/mediatek/clk-mt8366.c | 64 ++++++--------------------------------- drivers/clk/mediatek/clk-mt8512.c | 14 ++------- drivers/clk/mediatek/clk-mt8516.c | 7 +---- drivers/clk/mediatek/clk-mt8518.c | 7 +---- 8 files changed, 26 insertions(+), 150 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 5a4863049c5..13fee7a75a0 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -787,12 +787,7 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24), }; -static const struct mtk_clk_tree mt8183_infracfg_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = infra_clks, - .num_gates = ARRAY_SIZE(infra_clks), -}; +MTK_GATE_CLK_TREE(mt8183_infracfg_tree, infra_clks, ext_clock_rates); static const struct udevice_id mt8183_apmixed_compat[] = { { diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 90effc29ab2..3ede5e792d6 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -1619,12 +1619,7 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P, CLK_TOP_AES_MSDCFDE, 18), }; -static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = infracfg_ao_clks, - .num_gates = ARRAY_SIZE(infracfg_ao_clks), -}; +MTK_GATE_CLK_TREE(mt8188_infracfg_ao_clk_tree, infracfg_ao_clks, ext_clock_rates); static const struct mtk_gate_regs peri_ao_cg_regs = { .set_ofs = 0x10, @@ -1664,12 +1659,7 @@ static const struct mtk_gate pericfg_ao_clks[] = { GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_FMEM, CLK_TOP_466M_FMEM, 24), }; -static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = pericfg_ao_clks, - .num_gates = ARRAY_SIZE(pericfg_ao_clks), -}; +MTK_GATE_CLK_TREE(mt8188_pericfg_ao_clk_tree, pericfg_ao_clks, ext_clock_rates); static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { .set_ofs = 0xe08, @@ -1701,26 +1691,11 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = { GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6, CLK_TOP_I2C, 1), }; -static const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = imp_iic_wrap_c_clks, - .num_gates = ARRAY_SIZE(imp_iic_wrap_c_clks), -}; +MTK_GATE_CLK_TREE(mt8188_imp_iic_wrap_c_clk_tree, imp_iic_wrap_c_clks, ext_clock_rates); -static const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = imp_iic_wrap_w_clks, - .num_gates = ARRAY_SIZE(imp_iic_wrap_w_clks), -}; +MTK_GATE_CLK_TREE(mt8188_imp_iic_wrap_w_clk_tree, imp_iic_wrap_w_clks, ext_clock_rates); -static const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = imp_iic_wrap_en_clks, - .num_gates = ARRAY_SIZE(imp_iic_wrap_en_clks), -}; +MTK_GATE_CLK_TREE(mt8188_imp_iic_wrap_en_clk_tree, imp_iic_wrap_en_clks, ext_clock_rates); static const struct mtk_gate_regs vdo0_0_cg_regs = { .set_ofs = 0x104, @@ -2080,33 +2055,13 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_5(CLK_VDO1_DPI1_HDMI, CLK_TOP_VPP, 0), }; -static const struct mtk_clk_tree mt8188_vpp0_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = vpp0_clks, - .num_gates = ARRAY_SIZE(vpp0_clks), -}; +MTK_GATE_CLK_TREE(mt8188_vpp0_clk_tree, vpp0_clks, ext_clock_rates); -static const struct mtk_clk_tree mt8188_vpp1_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = vpp1_clks, - .num_gates = ARRAY_SIZE(vpp1_clks), -}; +MTK_GATE_CLK_TREE(mt8188_vpp1_clk_tree, vpp1_clks, ext_clock_rates); -static const struct mtk_clk_tree mt8188_vdo0_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = vdo0_clks, - .num_gates = ARRAY_SIZE(vdo0_clks), -}; +MTK_GATE_CLK_TREE(mt8188_vdo0_clk_tree, vdo0_clks, ext_clock_rates); -static const struct mtk_clk_tree mt8188_vdo1_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = vdo1_clks, - .num_gates = ARRAY_SIZE(vdo1_clks), -}; +MTK_GATE_CLK_TREE(mt8188_vdo1_clk_tree, vdo1_clks, ext_clock_rates); static const struct udevice_id mt8188_apmixed_compat[] = { { diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index de40821100e..fa1480e19bf 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -1596,12 +1596,7 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, CLK_TOP_MEM_466M, 31), }; -static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = infra_ao_clks, - .num_gates = ARRAY_SIZE(infra_ao_clks), -}; +MTK_GATE_CLK_TREE(mt8195_infracfg_ao_clk_tree, infra_ao_clks, ext_clock_rates); static const struct udevice_id mt8195_apmixed[] = { { diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 3fa030d7218..872de82d6f3 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -754,12 +754,7 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11), }; -static const struct mtk_clk_tree mt8365_infracfg_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = ifr_clks, - .num_gates = ARRAY_SIZE(ifr_clks), -}; +MTK_GATE_CLK_TREE(mt8365_infracfg_tree, ifr_clks, ext_clock_rates); static const struct udevice_id mt8365_apmixed_compat[] = { { diff --git a/drivers/clk/mediatek/clk-mt8366.c b/drivers/clk/mediatek/clk-mt8366.c index 533b769324c..cc490641b3d 100644 --- a/drivers/clk/mediatek/clk-mt8366.c +++ b/drivers/clk/mediatek/clk-mt8366.c @@ -1191,12 +1191,7 @@ static const struct mtk_gate infracfg_ao_reg_clks[] = { GATE_INFRACFG_AO_REG6(CLK_INFRACFG_AO_REGP_NFIECC_B, CLK_TOP_NFI_BCLK_SEL, 24), }; -static const struct mtk_clk_tree infracfg_ao_reg_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = infracfg_ao_reg_clks, - .num_gates = ARRAY_SIZE(infracfg_ao_reg_clks), -}; +MTK_GATE_CLK_TREE(infracfg_ao_reg_clks_tree, infracfg_ao_reg_clks, ext_clock_rates); static const struct mtk_gate_regs impc_cg_regs = { .set_ofs = 0xe08, @@ -1219,12 +1214,7 @@ static const struct mtk_gate impc_clks[] = { GATE_IMPC(CLK_IMPC_I2C9, CLK_TOP_I2CP_SEL, 7), }; -static const struct mtk_clk_tree impc_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = impc_clks, - .num_gates = ARRAY_SIZE(impc_clks), -}; +MTK_GATE_CLK_TREE(impc_clks_tree, impc_clks, ext_clock_rates); static const struct mtk_gate_regs impe_cg_regs = { .set_ofs = 0xe08, @@ -1241,12 +1231,7 @@ static const struct mtk_gate impe_clks[] = { GATE_IMPE(CLK_IMPE_I2C4, CLK_TOP_I2C_SEL, 1), }; -static const struct mtk_clk_tree impe_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = impe_clks, - .num_gates = ARRAY_SIZE(impe_clks), -}; +MTK_GATE_CLK_TREE(impe_clks_tree, impe_clks, ext_clock_rates); static const struct mtk_gate_regs mm0_cg_regs = { .set_ofs = 0x100, @@ -1321,12 +1306,7 @@ static const struct mtk_gate mm_clks[] = { GATE_MM1E(CLK_MM_32K, CLK_PAD_CLK32K, 19), }; -static const struct mtk_clk_tree mm_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = mm_clks, - .num_gates = ARRAY_SIZE(mm_clks), -}; +MTK_GATE_CLK_TREE(mm_clks_tree, mm_clks, ext_clock_rates); static const struct mtk_gate_regs dptx_phyd_sifslv_dig_glb_cg_regs = { .set_ofs = 0x8, @@ -1343,12 +1323,8 @@ static const struct mtk_gate dptx_phyd_sifslv_dig_glb_clks[] = { CLK_PAD_CLK26M, 0), }; -static const struct mtk_clk_tree dptx_phyd_sifslv_dig_glb_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = dptx_phyd_sifslv_dig_glb_clks, - .num_gates = ARRAY_SIZE(dptx_phyd_sifslv_dig_glb_clks), -}; +MTK_GATE_CLK_TREE(dptx_phyd_sifslv_dig_glb_clks_tree, + dptx_phyd_sifslv_dig_glb_clks, ext_clock_rates); static const struct mtk_gate_regs epdsys_config0_cg_regs = { .set_ofs = 0x100, @@ -1396,12 +1372,7 @@ static const struct mtk_gate epdsys_config_clks[] = { GATE_EPDSYS_CONFIG1(CLK_EPDSYS_DPI0_MM, CLK_TOP_EPD_SEL, 1), }; -static const struct mtk_clk_tree epdsys_config_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = epdsys_config_clks, - .num_gates = ARRAY_SIZE(epdsys_config_clks), -}; +MTK_GATE_CLK_TREE(epdsys_config_clks_tree, epdsys_config_clks, ext_clock_rates); static const struct mtk_gate_regs vde23_cg_regs = { .set_ofs = 0x8, @@ -1417,12 +1388,7 @@ static const struct mtk_gate vdec_gcon_clks[] = { GATE_VDE23(CLK_VDE2_LARB1_CKEN, CLK_TOP_VDEC_SEL, 0), }; -static const struct mtk_clk_tree vdec_gcon_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = vdec_gcon_clks, - .num_gates = ARRAY_SIZE(vdec_gcon_clks), -}; +MTK_GATE_CLK_TREE(vdec_gcon_clks_tree, vdec_gcon_clks, ext_clock_rates); static const struct mtk_gate_regs ipe_cg_regs = { .set_ofs = 0x4, @@ -1444,12 +1410,7 @@ static const struct mtk_gate ipesys_clks[] = { GATE_IPE(CLK_IPE_GALS, CLK_TOP_IPE_SEL, 8), }; -static const struct mtk_clk_tree ipesys_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = ipesys_clks, - .num_gates = ARRAY_SIZE(ipesys_clks), -}; +MTK_GATE_CLK_TREE(ipesys_clks_tree, ipesys_clks, ext_clock_rates); static const struct mtk_gate_regs cam_m_cg_regs = { .set_ofs = 0x4, @@ -1481,12 +1442,7 @@ static const struct mtk_gate camsys_main_clks[] = { GATE_CAM_M(CLK_CAM_M_PDA, CLK_TOP_CAM_SEL, 21), }; -static const struct mtk_clk_tree camsys_main_clks_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = camsys_main_clks, - .num_gates = ARRAY_SIZE(camsys_main_clks), -}; +MTK_GATE_CLK_TREE(camsys_main_clks_tree, camsys_main_clks, ext_clock_rates); static const struct udevice_id mt8366_apmixed_compat[] = { { diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index a0beae8fa5f..a6fbd6376b7 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -815,19 +815,9 @@ static const struct mtk_clk_tree mt8512_topckgen_clk_tree = { .type = MTK_CLK_TREE_TOPCKGEN, }; -static const struct mtk_clk_tree mt8512_topckgen_cg_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = top_clks, - .num_gates = ARRAY_SIZE(top_clks), -}; +MTK_GATE_CLK_TREE(mt8512_topckgen_cg_tree, top_clks, ext_clock_rates); -static const struct mtk_clk_tree mt8512_infracfg_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = infra_clks, - .num_gates = ARRAY_SIZE(infra_clks), -}; +MTK_GATE_CLK_TREE(mt8512_infracfg_tree, infra_clks, ext_clock_rates); static const struct udevice_id mt8512_apmixed_compat[] = { { diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index ea00b8dbca1..458aad3c5df 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -767,12 +767,7 @@ static const struct mtk_clk_tree mt8516_topckgen_clk_tree = { .type = MTK_CLK_TREE_TOPCKGEN, }; -static const struct mtk_clk_tree mt8516_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = top_clks, - .num_gates = ARRAY_SIZE(top_clks), -}; +MTK_GATE_CLK_TREE(mt8516_clk_tree, top_clks, ext_clock_rates); static const struct udevice_id mt8516_apmixed_compat[] = { { diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 4fef36f458a..f2472d039b0 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -1523,12 +1523,7 @@ static const struct mtk_clk_tree mt8518_topckgen_clk_tree = { .type = MTK_CLK_TREE_TOPCKGEN, }; -static const struct mtk_clk_tree mt8518_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), - .gates = top_clks, - .num_gates = ARRAY_SIZE(top_clks), -}; +MTK_GATE_CLK_TREE(mt8518_clk_tree, top_clks, ext_clock_rates); static const struct udevice_id mt8518_apmixed_compat[] = { { -- 2.55.0
