cadence_qspi_flash_reset() currently performs the OSPI flash GPIO reset
sequence directly. Switch it to use zynqmp_pm_ospi_flash_reset(),
routing the reset operation through the firmware abstraction layer.

This keeps firmware-specific handling out of the driver while preserving
the existing platform-specific behavior implemented by the helper.

Signed-off-by: Akshay Belsare <[email protected]>
---
 drivers/spi/cadence_ospi_versal.c | 41 +------------------------------
 1 file changed, 1 insertion(+), 40 deletions(-)

diff --git a/drivers/spi/cadence_ospi_versal.c 
b/drivers/spi/cadence_ospi_versal.c
index 6c388ab8208..f97bf744122 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -12,7 +12,6 @@
 #include <asm/gpio.h>
 #include <asm/cache.h>
 #include <cpu_func.h>
-#include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include "cadence_qspi.h"
 
@@ -159,45 +158,7 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct 
cadence_spi_priv *priv)
 #if !CONFIG_IS_ENABLED(DM_GPIO)
 int cadence_qspi_flash_reset(struct udevice *dev)
 {
-       /* CRP WPROT */
-       writel(0, WPROT_CRP);
-       /* GPIO Reset */
-       writel(0, RST_GPIO);
-
-       /* disable IOU write protection */
-       writel(0, WPROT_LPD_MIO);
-
-       /* set direction as output */
-       writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)),
-              BOOT_MODE_DIR);
-
-       /* Data output enable */
-       writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)),
-              BOOT_MODE_OUT);
-
-       /* IOU SLCR write enable */
-       writel(0, WPROT_PMC_MIO);
-
-       /* set MIO as GPIO */
-       writel(0x60, MIO_PIN_12);
-
-       /* Set value 1 to pin */
-       writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
-       udelay(10);
-
-       /* Disable Tri-state */
-       writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
-       udelay(5);
-
-       /* Set value 0 to pin */
-       writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
-       udelay(150);
-
-       /* Set value 1 to pin */
-       writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
-       udelay(1200);
-
-       return 0;
+       return zynqmp_pm_ospi_flash_reset();
 }
 #endif
 
-- 
2.25.1

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