On 9/15/26 10:00 AM, Julien Stephan wrote:
> This series adds a mipi-dsi PHY driver MR8183 compatible SoC such as the
> Genio-350 EVK. The driver is ported from the kernel driver.
>
> Patches 1 and 2 are preparatory patches: drivers/phy/ already carries 4
> MediaTek PHY drivers and this series adds another one, so collect them
> under drivers/phy/mediatek/ like the other vendors do. Kconfig symbol
> names are unchanged, so no defconfig is affected. Also sort entries in
> Makefiles and Kconfig.
>
> Patch 3 adds the MIPI DSI PHY driver itself, supporting MT8183-compatible
> SoCs, based on kernel commit 2ec9c210c1f9 ("phy: mediatek: Add support
> for MT8196 MIPI DSI PHY").
>
> Two deliberate deviations from the kernel driver:
>
> - The kernel registers the MIPI TX PLL as a clock provider and hands it
> to the DSI host as its "hs" clock. U-Boot has no consumer for that
> clock, so the PLL clk_ops are folded into the PHY ops:
> determine_rate + set_rate become .configure(), and prepare_enable
> becomes .power_on().
>
> - The kernel reads per-lane impedance trim codes from the
> "calibration-data" nvmem cell. MT8365 doe snot have that cell in DT yet,
s/doe snot/does not/ (makes me imagine an AI generated image of a deer with
a runny nose)
> so rt_code[] stays zeroed and the SoC layer falls back to the same
> 0x210 mid-scale default the kernel uses when the cell is absent. This
> can be wired up later.
>
> Tested on Genio 350 (MT8365). The DSI host side that consumes this PHY
> is sent separately to ease review
>
Most of my comments were just for typos, so could fix up while applying if
nothing more serious comes up.
