Add the missing CLK_INFRA_SSPM, CLK_INFRA_SSPM_BUS_HCLK,
CLK_INFRA_SSPM_26M_SELF and CLK_INFRA_SSPM_32K_SELF gates, based on the
Linux driver, along with the 32 kHz external clock that is the parent of
the last one. Move CLK_INFRA_USB and CLK_INFRA_DEVMPU_BCLK to their
places in ID order.
The common MediaTek clock code looks a gate up by using the clock ID as
an index into the gate array, so the array must be sorted by ID and have
no holes. infra_clks[] followed the register layout instead and was
missing the four SSPM gates, so every ID from 51 up selected the wrong
gate.
Fixes: c9d7e79f02ef ("clk: mediatek: Add MT8183 clock driver")
Signed-off-by: David Lechner <[email protected]>
---
drivers/clk/mediatek/clk-mt8183.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8183.c
b/drivers/clk/mediatek/clk-mt8183.c
index 08e06c60f68..aff5d629c30 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -18,10 +18,12 @@
#define MT8183_PLL_FMIN (1500UL * MHZ)
enum {
+ CLK_PAD_CLK32K,
CLK_PAD_CLK26M,
};
static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK32K] = 32000,
[CLK_PAD_CLK26M] = 26 * MHZ,
};
@@ -683,6 +685,14 @@ static const struct mtk_gate_regs infra3_cg_regs = {
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
+#define GATE_INFRA3_EXT(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \
+ }
+
static const struct mtk_gate infra_clks[] = {
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_PMIC_TMR, CLK_TOP_MUX_AXI, 0),
@@ -737,11 +747,9 @@ static const struct mtk_gate infra_clks[] = {
GATE_INFRA1(CLK_INFRA_CCIF_MD, CLK_TOP_MUX_AXI, 26),
GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, CLK_TOP_MUX_DXCC, 27),
GATE_INFRA1(CLK_INFRA_DXCC_AO, CLK_TOP_MUX_DXCC, 28),
- GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, CLK_TOP_MUX_AXI, 30),
GATE_INFRA1(CLK_INFRA_DRAMC_F26M, CLK_TOP_CLK26M, 31),
/* INFRA2 */
GATE_INFRA2(CLK_INFRA_IRTX, CLK_TOP_CLK26M, 0),
- GATE_INFRA2(CLK_INFRA_USB, CLK_TOP_MUX_USB_TOP, 1),
GATE_INFRA2(CLK_INFRA_DISP_PWM, CLK_TOP_MUX_AXI, 2),
GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, CLK_TOP_MUX_AXI, 3),
GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4),
@@ -754,7 +762,9 @@ static const struct mtk_gate infra_clks[] = {
GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, CLK_TOP_MUX_FUFS, 12),
GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, CLK_TOP_MUX_FUFS, 13),
GATE_INFRA2(CLK_INFRA_MD32_BCLK, CLK_TOP_MUX_AXI, 14),
+ GATE_INFRA2(CLK_INFRA_SSPM, CLK_TOP_MUX_SSPM, 15),
GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, CLK_TOP_MUX_AXI, 16),
+ GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, CLK_TOP_MUX_AXI, 17),
GATE_INFRA2(CLK_INFRA_I2C5, CLK_TOP_MUX_I2C, 18),
GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, CLK_TOP_MUX_I2C, 19),
GATE_INFRA2(CLK_INFRA_I2C5_IMM, CLK_TOP_MUX_I2C, 20),
@@ -772,10 +782,14 @@ static const struct mtk_gate infra_clks[] = {
GATE_INFRA3(CLK_INFRA_MSDC0_SELF, CLK_TOP_MUX_MSDC50_0, 0),
GATE_INFRA3(CLK_INFRA_MSDC1_SELF, CLK_TOP_MUX_MSDC50_0, 1),
GATE_INFRA3(CLK_INFRA_MSDC2_SELF, CLK_TOP_MUX_MSDC50_0, 2),
+ GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, CLK_TOP_CLK26M, 3),
+ GATE_INFRA3_EXT(CLK_INFRA_SSPM_32K_SELF, CLK_PAD_CLK32K, 4),
GATE_INFRA3(CLK_INFRA_UFS_AXI, CLK_TOP_MUX_AXI, 5),
GATE_INFRA3(CLK_INFRA_I2C6, CLK_TOP_MUX_I2C, 6),
GATE_INFRA3(CLK_INFRA_AP_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 7),
GATE_INFRA3(CLK_INFRA_MD_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 8),
+ GATE_INFRA2(CLK_INFRA_USB, CLK_TOP_MUX_USB_TOP, 1),
+ GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, CLK_TOP_MUX_AXI, 30),
GATE_INFRA3(CLK_INFRA_CCIF2_AP, CLK_TOP_MUX_AXI, 16),
GATE_INFRA3(CLK_INFRA_CCIF2_MD, CLK_TOP_MUX_AXI, 17),
GATE_INFRA3(CLK_INFRA_CCIF3_AP, CLK_TOP_MUX_AXI, 18),
--
2.43.0
