Move the TOP3 gates after the TOP4 gates in top_clks[].
The common MediaTek clock code looks a gate up by using the clock ID as
an index into the gate array, so the array must be sorted by ID. The
TOP3 gates (IDs 67 to 70) came before the TOP4 gates (IDs 57 to 66), so
all of these IDs selected the wrong gate.
Fixes: 907240077516 ("clk: mediatek: add driver for MT8518")
Signed-off-by: David Lechner <[email protected]>
---
drivers/clk/mediatek/clk-mt8518.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8518.c
b/drivers/clk/mediatek/clk-mt8518.c
index 70dc659419c..f875d4fcdd5 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -1452,11 +1452,6 @@ static const struct mtk_gate top_clks[] = {
GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
- /* TOP3 */
- GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
- GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
- GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
- GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
/* TOP4 */
GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
@@ -1468,6 +1463,11 @@ static const struct mtk_gate top_clks[] = {
GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
+ /* TOP3 */
+ GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
/* TOP5 */
GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
--
2.43.0
