Deasserting DDR retention pin is quite similar from J7200, J784s4 and j721s2 SoCs.
Instead of duplicating almost the same code, add it in lpm-common.c. NB: On J7200, there's a latch, so the clock needs to be toggled. Reviewed-by: Udit Kumar <[email protected]> Signed-off-by: Richard Genoud (TI) <[email protected]> --- arch/arm/mach-k3/lpm-common.h | 2 ++ arch/arm/mach-k3/r5/lpm-common.c | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/mach-k3/lpm-common.h b/arch/arm/mach-k3/lpm-common.h index 27a27065442c..17352b06353f 100644 --- a/arch/arm/mach-k3/lpm-common.h +++ b/arch/arm/mach-k3/lpm-common.h @@ -15,6 +15,8 @@ void __noreturn do_resume(void); void lpm_process(void); int save_lpm_region_idx(unsigned int image_id, unsigned long image_start); +void k3_deassert_ddr_ret(const char *pmic_name, unsigned int ddr_ret_val, + unsigned int ddr_ret_clk, bool toggle); void k3_set_lpm_core_bus_node_path(const char *node_path); void k3_set_lpm_core_compatible(const char *compatible); #else diff --git a/arch/arm/mach-k3/r5/lpm-common.c b/arch/arm/mach-k3/r5/lpm-common.c index 5d484f6df037..f1d16f38157f 100644 --- a/arch/arm/mach-k3/r5/lpm-common.c +++ b/arch/arm/mach-k3/r5/lpm-common.c @@ -46,6 +46,33 @@ enum k3_resume_state { K3_RESUME_STATE_RESUMING }; +#define GPIO_OUT_1 0x3D +void k3_deassert_ddr_ret(const char *pmic_name, unsigned int ddr_ret_val, + unsigned int ddr_ret_clk, bool toggle) +{ + struct udevice *pmic; + int regval; + int err; + + err = uclass_get_device_by_name(UCLASS_PMIC, pmic_name, &pmic); + if (err) { + printf("Getting %s init failed: %d\n", pmic_name, err); + return; + } + + /* Set DDR_RET Signal Low on PMIC */ + regval = pmic_reg_read(pmic, GPIO_OUT_1) & ~ddr_ret_val; + pmic_reg_write(pmic, GPIO_OUT_1, regval); + + if (toggle) { + /* Now toggle the CLK of the latch for DDR retention */ + pmic_reg_write(pmic, GPIO_OUT_1, regval | ddr_ret_clk); + pmic_reg_write(pmic, GPIO_OUT_1, regval & ~ddr_ret_clk); + pmic_reg_write(pmic, GPIO_OUT_1, regval | ddr_ret_clk); + pmic_reg_write(pmic, GPIO_OUT_1, regval & ~ddr_ret_clk); + } +} + bool j7xx_board_is_resuming(void) { static enum k3_resume_state k3_resuming; -- 2.55.0
