Change the compatible of the display clock controller from "mediatek,mt8189-dispsys" to "mediatek,mt8189-mmsys" and rename the node to syscon@14000000 with the mmsys label.
The display clock gates live in the mmsys register block at 0x14000000. The proposed Linux binding for MT8189 adds "mediatek,mt8189-mmsys" to mediatek,mmsys.yaml, which requires a "syscon@" node name, a "syscon" fallback and #clock-cells. This follows MT8188 and MT8195, where the vdosys0 mmsys node is also the display clock provider. The old "mediatek,mt8189-dispsys" name is not in any upstream binding. The mmsys label matches the other SoCs with a single mmsys block at 0x14000000 (MT8183, MT8186, MT8192 and MT8365). Update the one reference in the power controller node. Signed-off-by: David Lechner <[email protected]> --- arch/arm/dts/mt8189.dtsi | 6 +++--- drivers/clk/mediatek/clk-mt8189.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi index f3a350c51b8..656f5488c72 100644 --- a/arch/arm/dts/mt8189.dtsi +++ b/arch/arm/dts/mt8189.dtsi @@ -169,7 +169,7 @@ power-domain@MT8189_POWER_DOMAIN_DISP { reg = <MT8189_POWER_DOMAIN_DISP>; clocks = <&topckgen_clk CLK_TOP_DISP0_SEL>, - <&dispsys_config_clk CLK_MM_SMI_LARB>; + <&mmsys CLK_MM_SMI_LARB>; clock-names = "disp", "ss-disp"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; @@ -398,8 +398,8 @@ #clock-cells = <1>; }; - dispsys_config_clk: clock-controller@14000000 { - compatible = "mediatek,mt8189-dispsys", "syscon"; + mmsys: syscon@14000000 { + compatible = "mediatek,mt8189-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index a5cb387772a..ece7d739f86 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -2000,7 +2000,7 @@ static const struct udevice_id mt8189_clk_compat[] = { .data = (ulong)&imp_clks_tree, }, { - .compatible = "mediatek,mt8189-dispsys", + .compatible = "mediatek,mt8189-mmsys", .data = (ulong)&mm_clks_tree, }, { --- base-commit: e3ed6c6436abc18af0c7a0298ac72f83ebf2b5d1 change-id: 20260923-mtk-clk-mt8189-mmsys-7fe9bacc1af6 Best regards, -- David Lechner <[email protected]>
