Add support for resuming from suspend in board_init_f.
The resume state of the SOC is identified and LPM resume
sequence is followed accordingly.

First, set LPM core bus path and compatible needed by extract_lpm_region
to find lpm-metadata memory region (at boot and at resume time)

Then, add the board specific part of the exit retention sequence for
k3-ddrss following the DDR resume sequence:
   - exit DDR from retention
   - de-assert the DDR_RET pin
   - restore DDR max frequency
   - exit DDR from low power

The self-refresh exit sequence is performed in a loop for each DDR
controller. (J784S4 has 4 DDR controllers and J742S2 has only 2)

Select the number of ddr controllers on the basis of
CONFIG_TARGET_J742S2_R5_EVM build flag.

Finally:
   - Extract context address from devicetree
   - Power on the rproc cluster power domain.
   - Ask TIFS to authenticate the certificates attached to saved images
     of ATF, OPTEE and DM and apply the firewalls in it.
   - Send the context address to TIFS.
   - Ask TIFS to firewall the context address area.
   - Ask TIFS to decrypt and restore TFA.
   - Ask TIFS to resume TFA.
   - Power on the rproc power domain.
   - Jump to DM firmware.
(All those steps are done in do_resume())

Co-developed-by: Gregory CLEMENT (TI) <[email protected]>
Signed-off-by: Gregory CLEMENT (TI) <[email protected]>
Co-developed-by: Thomas Richard (TI) <[email protected]>
Signed-off-by: Thomas Richard (TI) <[email protected]>
Co-developed-by: Prasanth Babu Mantena <[email protected]>
Signed-off-by: Prasanth Babu Mantena <[email protected]>
Co-developed-by: Abhash Kumar Jha <[email protected]>
Signed-off-by: Abhash Kumar Jha <[email protected]>
Signed-off-by: Richard Genoud (TI) <[email protected]>
---
 arch/arm/mach-k3/j784s4/j784s4_init.c | 52 +++++++++++++++++++++++++--
 board/ti/j784s4/evm.c                 |  3 +-
 2 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c 
b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 507b7ab685ad..84e7d6d659a8 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -18,11 +18,21 @@
 #include <mmc.h>
 #include <remoteproc.h>
 #include <k3_bist.h>
+#include <power/pmic.h>
+#include <mach/k3-ddr.h>
 
 #include "../sysfw-loader.h"
 #include "../common.h"
+#include "../lpm-common.h"
 
-#define J784S4_MAX_DDR_CONTROLLERS     4
+#if IS_ENABLED(CONFIG_TARGET_J742S2_R5_EVM)
+#define MAX_DDR_CONTROLLERS    2
+#else
+#define MAX_DDR_CONTROLLERS    4
+#endif
+
+/* DDR retention bits */
+#define DDR_RET_VAL BIT(5)
 
 #define CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL       0x001082e4
 #define AUDIO_REFCLK1_DEFAULT                  0x1c
@@ -279,20 +289,58 @@ void k3_mem_init(void)
        int ret, ctrl = 0;
 
        if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
+               struct udevice *devs[MAX_DDR_CONTROLLERS];
+               struct k3_ddrss_regs regs[MAX_DDR_CONTROLLERS];
+
                ret = uclass_get_device(UCLASS_RAM, 0, &dev);
                if (ret)
                        panic("DRAM 0 init failed: %d\n", ret);
+
+               devs[0] = dev;
                ctrl++;
 
-               while (ctrl < J784S4_MAX_DDR_CONTROLLERS) {
+               while (ctrl < MAX_DDR_CONTROLLERS) {
                        ret = uclass_next_device_err(&dev);
                        if (ret == -ENODEV)
                                break;
 
                        if (ret)
                                panic("DRAM %d init failed: %d\n", ctrl, ret);
+                       devs[ctrl] = dev;
                        ctrl++;
                }
+
+               k3_set_lpm_core_bus_node_path("/bus@100000/bus@28380000");
+               k3_set_lpm_core_compatible("ti,j721s2-r5f");
+
+               if (j7xx_board_is_resuming()) {
+                       /* exit DDRs from retention */
+                       for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++) {
+                               k3_ddrss_lpddr4_exit_retention(devs[ctrl],
+                                                              &regs[ctrl]);
+                       }
+
+                       /* de-assert DDR_RET pin */
+                       k3_deassert_ddr_ret("pmic@48", DDR_RET_VAL, 0, false);
+
+                       /* restore DDR max frequency */
+                       for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++)
+                               k3_ddrss_lpddr4_change_freq(devs[ctrl]);
+
+                       /* exit DDR from low power */
+                       for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++) {
+                               k3_ddrss_lpddr4_exit_low_power(devs[ctrl],
+                                                              &regs[ctrl]);
+                       }
+                       printf("Initialized %d DRAM controllers\n", ctrl);
+
+                       /*
+                        * The DM (PDK) doesn't support being started with
+                        * caches enabled, and there no gain enabling them here
+                        * and disabling them just before jumping to DM
+                        */
+                       do_resume();
+               }
                printf("Initialized %d DRAM controllers\n", ctrl);
        }
 
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index 5e9b9944a15f..269ea0801fb4 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -61,7 +61,8 @@ int board_late_init(void)
 }
 #endif
 
-#if (IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_J784S4_R5_EVM))
+#if (IS_ENABLED(CONFIG_SPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_J784S4_R5_EVM) 
|| \
+                                     IS_ENABLED(CONFIG_TARGET_J742S2_R5_EVM)))
 void clear_isolation(void)
 {
        int ret;
-- 
2.55.0

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