[add Beleswar]
Le 09/10/2026 à 01:40, Tom Rini a écrit :
On Thu, Sep 24, 2026 at 02:35:11PM +0200, Richard Genoud (TI) wrote:
This series allows J7200/J721s2/J784s4/J722s to resume from suspend.
On those SoCs, a magic value is set in a PMIC register by the DM
firmware just before suspend, then everything but the PMIC and DDR is
powered off.
At resume/boot time, the magic value has to be read back by U-Boot SPL in
order to know if we are indeed in a resume situation.
That's the purpose of j7xx_board_is_resuming() introduced here.
Then, if the SoC is resuming, the DDR has to be brought out of
retention, at full speed and get out of low power mode.
Between those steps, the DDR_RET pin has to be de-asserted. But the
DDR_RET pins of all DDR chips are tied together on a single GPIO, so
it's impossible to resume one DDR chip after the other, they must be all
resumed at once.
That's why it's orchestrated from board_init_f() and not in the k3ddrss
driver.
Once the DDR is fully functional, the next steps are:
- retrieve the LPM memory region from DTS
- authenticate certificates from LPM memory region and apply firewalls
- ask TIFS to restore TFA and its own minimal context
- start TFA on remote proc
- load and jump to DM
Disclaimer:
---------
There's a potential attack vector in this sequence, because OPTEE could
be modified before being reloaded.
Also, if the certificate replay is skipped, then TFA can be read from
MSMC.
Patch 1 and 2 are from AM62 LPM series:
https://lore.kernel.org/u-boot/20260105-topic-am62-ioddr-v2025-04-rc1-v9-0-7e33f2c77...@baylibre.com/
Patch 1 adds support for DDR in self-refresh for am62/j722s
Patch 2 adds capability to call TI_SCI_MSG_MIN_CONTEXT_RESTORE
Patches 3-5 add LPM helpers for all SoCs
Patch 6 adds the resume detection for all SoCs
Patch 7 adds common code for DDR retention pin
Patch 8 enables GTC at resume
Patch 9 detects IO+DDR resume state for j7200/j784s4
Patch 10 stores the wakeup reason in MCU_PSRAM0_RAM for j7200/j784s4
Patch 11 sets the PMIC NSLEEP triggers
Patches 12-14 add the DDR resume sequence for all SoCs
Patches 15-18 add the resume flow for all SoCs
Patch 19 updates the pm-cfg and schema to a new version
Patch 20 removes now unneeded background firewall on DDR for j7200/j784s4
Patch 21 extends the firewall for ATF region to TIFS
Patch 22 add the resume flow documentation
Tested on J722s HS-FS, J7200 GP, J784s4 GP, J721s2 GP
https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/lpm.html#tisci-msg-min-context-restore
It needs lpm_memory_regions described in DTS [updated to v4]:
https://lore.kernel.org/lkml/[email protected]/T/#t
It also needs a bootph-pre-ram property in PMIC-B for j721s2:
https://lore.kernel.org/linux-arm-kernel/20260429-k3-j721s2-som-bootph-pre-ram-pmic-4c-v2-1-31a0e7677...@bootlin.com/
Given these needs, should it wait to be merged until we can pull in a
devicetree-rebasing tag that contains it all? Thanks.
The bootph-ram property has been merged.
And for the lpm_memory_regions, I've talked with Beleswar during ELCE,
he'll have a look at it.
That said, I agree that it should be at least fully acked in Linux repo
before merging it to u-boot
Thanks!
Regards,
Richard
