Replace the per-ops enable and disable callbacks with one mtk_clk_enable() and mtk_clk_disable() that handle a PLL, a mux or a gate according to the clock ID, and do nothing for the other types.
The PLL sequences move into mtk_pll_enable() and mtk_pll_disable(), and the mux helpers lose their own type check since the callers now make it. The checks follow the order of the tables in struct mtk_clk_tree. The order does not matter, as the ID ranges of a tree do not overlap, including the apmixedsys trees that define gates next to their PLLs. Fixed clocks and fixed factors cannot be switched, which is what the removed mtk_dummy_enable() and the mux fallback already reported. No functional change. Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mtk.c | 129 +++++++++++++---------------------------- 1 file changed, 40 insertions(+), 89 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d93c19c74db..ac173dc48cd 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -195,11 +195,6 @@ static int mtk_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) return 0; } -static int mtk_dummy_enable(struct clk *clk) -{ - return 0; -} - static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate) { u32 bit = BIT(gate->shift); @@ -609,21 +604,11 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) return __mtk_pll_recalc_rate(pll, xtal_rate, pcw, postdiv); } -static int mtk_apmixedsys_enable(struct clk *clk) +static int mtk_pll_enable(struct mtk_clk_priv *priv, + const struct mtk_pll_data *pll) { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_pll_data *pll; - const struct mtk_gate *gate; u32 r; - /* GATE handling */ - if (mtk_clk_id_is_gate(priv->tree, clk->id)) { - gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - return mtk_gate_enable(priv->base, gate); - } - - pll = &priv->tree->plls[clk->id]; - r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON; writel(r, priv->base + pll->pwr_reg); udelay(1); @@ -647,21 +632,11 @@ static int mtk_apmixedsys_enable(struct clk *clk) return 0; } -static int mtk_apmixedsys_disable(struct clk *clk) +static int mtk_pll_disable(struct mtk_clk_priv *priv, + const struct mtk_pll_data *pll) { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_pll_data *pll; - const struct mtk_gate *gate; u32 r; - /* GATE handling */ - if (mtk_clk_id_is_gate(priv->tree, clk->id)) { - gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - return mtk_gate_disable(priv->base, gate); - } - - pll = &priv->tree->plls[clk->id]; - if (pll->flags & CLK_PLL_HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r &= ~pll->rst_bar_mask; @@ -763,9 +738,6 @@ static int mtk_clk_mux_enable(struct clk *clk) const struct mtk_composite *mux; u32 val; - if (!mtk_clk_id_is_mux(priv->tree, clk->id)) - return 0; - mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; if (mux->gate_shift < 0) return 0; @@ -790,29 +762,12 @@ static int mtk_clk_mux_enable(struct clk *clk) return 0; } -static int mtk_topckgen_enable(struct clk *clk) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_clk_tree *tree = priv->tree; - - if (mtk_clk_id_is_gate(tree, clk->id)) { - const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; - - return mtk_gate_enable(priv->base, gate); - } - - return mtk_clk_mux_enable(clk); -} - static int mtk_clk_mux_disable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux; u32 val; - if (!mtk_clk_id_is_mux(priv->tree, clk->id)) - return 0; - mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; if (mux->gate_shift < 0) return 0; @@ -830,18 +785,40 @@ static int mtk_clk_mux_disable(struct clk *clk) return 0; } -static int mtk_topckgen_disable(struct clk *clk) +static int mtk_clk_enable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (mtk_clk_id_is_gate(tree, clk->id)) { - const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; + if (mtk_clk_id_is_pll(tree, clk->id)) + return mtk_pll_enable(priv, &tree->plls[clk->id]); - return mtk_gate_disable(priv->base, gate); - } + if (mtk_clk_id_is_mux(tree, clk->id)) + return mtk_clk_mux_enable(clk); + + if (mtk_clk_id_is_gate(tree, clk->id)) + return mtk_gate_enable(priv->base, + &tree->gates[clk->id - tree->gates_offs]); + + return 0; +} + +static int mtk_clk_disable(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_clk_tree *tree = priv->tree; + + if (mtk_clk_id_is_pll(tree, clk->id)) + return mtk_pll_disable(priv, &tree->plls[clk->id]); + + if (mtk_clk_id_is_mux(tree, clk->id)) + return mtk_clk_mux_disable(clk); + + if (mtk_clk_id_is_gate(tree, clk->id)) + return mtk_gate_disable(priv->base, + &tree->gates[clk->id - tree->gates_offs]); - return mtk_clk_mux_disable(clk); + return 0; } static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) @@ -917,32 +894,6 @@ static void mtk_topckgen_dump(struct udevice *dev) /* infrasys functions */ -static int mtk_clk_infrasys_enable(struct clk *clk) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate; - - /* MUX handling */ - if (!mtk_clk_id_is_gate(priv->tree, clk->id)) - return mtk_clk_mux_enable(clk); - - gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - return mtk_gate_enable(priv->base, gate); -} - -static int mtk_clk_infrasys_disable(struct clk *clk) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate; - - /* MUX handling */ - if (!mtk_clk_id_is_gate(priv->tree, clk->id)) - return mtk_clk_mux_disable(clk); - - gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - return mtk_gate_disable(priv->base, gate); -} - static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); @@ -1019,8 +970,8 @@ static void mtk_infrasys_dump(struct udevice *dev) const struct clk_ops mtk_clk_apmixedsys_ops = { .of_xlate = mtk_clk_of_xlate, - .enable = mtk_apmixedsys_enable, - .disable = mtk_apmixedsys_disable, + .enable = mtk_clk_enable, + .disable = mtk_clk_disable, .set_rate = mtk_apmixedsys_set_rate, .get_rate = mtk_apmixedsys_get_rate, #if CONFIG_IS_ENABLED(CMD_CLK) @@ -1030,8 +981,8 @@ const struct clk_ops mtk_clk_apmixedsys_ops = { const struct clk_ops mtk_clk_fixed_pll_ops = { .of_xlate = mtk_clk_of_xlate, - .enable = mtk_dummy_enable, - .disable = mtk_dummy_enable, + .enable = mtk_clk_enable, + .disable = mtk_clk_disable, .get_rate = mtk_topckgen_get_rate, #if CONFIG_IS_ENABLED(CMD_CLK) .dump = mtk_topckgen_dump, @@ -1040,8 +991,8 @@ const struct clk_ops mtk_clk_fixed_pll_ops = { const struct clk_ops mtk_clk_topckgen_ops = { .of_xlate = mtk_clk_of_xlate, - .enable = mtk_topckgen_enable, - .disable = mtk_topckgen_disable, + .enable = mtk_clk_enable, + .disable = mtk_clk_disable, .get_rate = mtk_topckgen_get_rate, .set_parent = mtk_common_clk_set_parent, #if CONFIG_IS_ENABLED(CMD_CLK) @@ -1051,8 +1002,8 @@ const struct clk_ops mtk_clk_topckgen_ops = { const struct clk_ops mtk_clk_infrasys_ops = { .of_xlate = mtk_clk_of_xlate, - .enable = mtk_clk_infrasys_enable, - .disable = mtk_clk_infrasys_disable, + .enable = mtk_clk_enable, + .disable = mtk_clk_disable, .get_rate = mtk_infrasys_get_rate, .set_parent = mtk_common_clk_set_parent, #if CONFIG_IS_ENABLED(CMD_CLK) -- 2.43.0
