Add the device trees for the MT2824 SoC (mt2824.dtsi) and the MT5824 EVB board (mt5824-evb.dts). The SoC integrates:
- a dual-core Andes AX45MP with 256 KB unified L2 cache - PLIC, PLIC SW and PLMT interrupt and timer controllers - a DesignWare-derived SDHCI controller - an ATCSPI200 QSPI controller with a 32 MiB Macronix NOR flash exposed as a memory-mapped device through nvmxip - a DDR controller with its firmware mapped through a "fw" reg entry The u-boot.dtsi overlay marks the nodes used by the SPL with bootph-pre-ram and describes the binman FIT image packing OpenSBI, U-Boot and the device tree. Signed-off-by: Benoît Monin <[email protected]> --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/mt2824-u-boot.dtsi | 66 ++++++++++++ arch/riscv/dts/mt2824.dtsi | 219 ++++++++++++++++++++++++++++++++++++++ arch/riscv/dts/mt5824-evb.dts | 34 ++++++ 4 files changed, 320 insertions(+) diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 8ba75fdb9f5..b13e0436b98 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb +dtb-$(CONFIG_TARGET_METANOIA_MT5824_EVB) += mt5824-evb.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_MILKV_DUO_256M) += sg2002-milkv-duo256m.dtb diff --git a/arch/riscv/dts/mt2824-u-boot.dtsi b/arch/riscv/dts/mt2824-u-boot.dtsi new file mode 100644 index 00000000000..8155fe580eb --- /dev/null +++ b/arch/riscv/dts/mt2824-u-boot.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 Metanoia Communications Inc. All rights reserved. + */ + +#include "binman.dtsi" + +/ { + cpus { + bootph-pre-ram; + + cpu0: cpu@0 { + bootph-pre-ram; + }; + + cpu1: cpu@1 { + bootph-pre-ram; + }; + }; + + l2: l2-cache@a000000 { + bootph-pre-ram; + }; + + soc { + bootph-pre-ram; + + plicsw: interrupt-controller@c800000 { + bootph-pre-ram; + }; + + plmt0@c400000 { + bootph-pre-ram; + }; + + rst: reset-controller@1000000c { + bootph-pre-ram; + }; + + ddrc: ddrc@10060000 { + compatible = "metanoia,mt2824-ddrc"; + reg = <0x0 0x10060000 0x0 0x1000>, + <0x0 0x14000000 0x0 0x800000>, + <0x0 0x70080000 0x0 0x20000>; + reg-names = "ctrl", "phy", "fw"; + resets = <&rst 17>; + bootph-pre-ram; + }; + + serial0: serial@100e0000 { + bootph-pre-ram; + }; + + nvmxip@20000000 { + compatible = "nvmxip,qspi"; + reg = <0x0 0x20000000 0x0 0x2000000>; + lba_shift = <9>; + lba = <65536>; + bootph-pre-ram; + }; + + mmcsd: mmc@4100000 { + bootph-pre-ram; + }; + }; +}; diff --git a/arch/riscv/dts/mt2824.dtsi b/arch/riscv/dts/mt2824.dtsi new file mode 100644 index 00000000000..cd11a949f22 --- /dev/null +++ b/arch/riscv/dts/mt2824.dtsi @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 Metanoia Communications Inc. All rights reserved. + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Metanoia MT2824"; + compatible = "metanoia,mt2824"; + + aliases { + uart0 = &serial0; + }; + + cpus: cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <20000000>; + + cpu0: cpu@0 { + device_type = "cpu"; + reg = <0x00>; + status = "okay"; + compatible = "andestech,ax45mp", "riscv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type = "riscv,sv39"; + clock-frequency = <900000000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x100>; + i-cache-line-size = <0x40>; + i-cache-block-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-sets = <0x80>; + d-cache-line-size = <0x40>; + d-cache-block-size = <0x40>; + next-level-cache = <&l2>; + + cpu0intc: interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x01>; + status = "okay"; + compatible = "andestech,ax45mp", "riscv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type = "riscv,sv39"; + clock-frequency = <900000000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x100>; + i-cache-line-size = <0x40>; + i-cache-block-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-sets = <0x80>; + d-cache-line-size = <0x40>; + d-cache-block-size = <0x40>; + next-level-cache = <&l2>; + + cpu1intc: interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; + }; + }; + }; + + l2: l2-cache@a000000 { + compatible = "metanoia,mt2824-ax45mp-cache", + "andestech,ax45mp-cache", + "cache"; + reg = <0x00 0xa000000 0x00 0x40000>; + cache-line-size = <64>; + cache-level = <2>; + cache-size = <0x40000>; + cache-sets = <1024>; + cache-unified; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&plic>; + }; + + clocks { + ext_clk: ext-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "ext-clk"; + }; + + pclk: platform-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <900000000>; + clock-output-names = "platform-clock"; + }; + + pclk_div2: platform-clock-div2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <450000000>; + clock-output-names = "platform-clock-div2"; + }; + + pclk_div4: platform-clock-div4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <225000000>; + clock-output-names = "platform-clock-div4"; + }; + + pll_soc_out3: pll-soc-out3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <180000000>; + clock-output-names = "pll-soc-out3"; + }; + + usb_otg_ahb_clk: clock-usb-otg-ahb { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + clock-output-names = "otg"; + }; + }; + + soc: soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + interrupt-parent = <&plic>; + ranges; + + plic: interrupt-controller@c000000 { + compatible = "metanoia,mt2824-plic", "andestech,nceplic100"; + reg = <0x0 0x0c000000 0x0 0x400000>; + interrupts-extended = <&cpu0intc 0x0b>, <&cpu0intc 0x09>, + <&cpu1intc 0x0b>, <&cpu1intc 0x09>; + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x02>; + riscv,ndev = <0x47>; + }; + + plicsw: interrupt-controller@c800000 { + compatible = "metanoia,mt2824-plicsw", "andestech,plicsw"; + reg = <0x00 0x0c800000 0x00 0x400000>; + interrupts-extended = + <&cpu0intc IRQ_TYPE_EDGE_BOTH>, + <&cpu1intc IRQ_TYPE_EDGE_BOTH>; + }; + + plmt0@c400000 { + compatible = "metanoia,mt2824-plmt", "andestech,plmt0"; + reg = <0x0 0x0c400000 0x0 0x00400000>; + interrupts-extended = <&cpu0intc 0x07>, + <&cpu1intc 0x07>; + }; + + reboot: reboot@10000004 { + compatible = "metanoia,mt2824-reboot"; + reg = <0x0 0x10000004 0x0 0x08>; + }; + + rst: reset-controller@1000000c { + #reset-cells = <1>; + compatible = "metanoia,mt2824-reset"; + reg = <0x0 0x1000000c 0x0 0x04>; + }; + + serial0: serial@100e0000 { + compatible = "ns16550a"; + reg = <0x00 0x100e0000 0x00 0x1000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&plic>; + clocks = <&pclk_div4>; + current-speed = <115200>; + reg-shift = <0x02>; + reg-offset = <0x20>; + reg-io-width = <0x04>; + }; + + qspi: spi@10120000 { + compatible = "metanoia,mt2824-spi"; + reg = <0x00 0x10120000 0x00 0x10000>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&plic>; + #address-cells = <0x01>; + #size-cells = <0x00>; + num-cs = <0x01>; + clocks = <&pll_soc_out3>; + clock-names = "spi_clk_src"; + }; + + mmcsd: mmc@4100000 { + compatible = "metanoia,mt2824-dwcmshc"; + max-frequency = <200000000>; + clocks = <&pll_soc_out3>; + clock-names = "core"; + reg = <0x0 0x04100000 0x0 0x00100000>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&plic>; + sdhci-caps-mask = <0x80000006 0x00000000>; + bus-width = <4>; + disable-wp; + }; + }; +}; diff --git a/arch/riscv/dts/mt5824-evb.dts b/arch/riscv/dts/mt5824-evb.dts new file mode 100644 index 00000000000..207051e8a14 --- /dev/null +++ b/arch/riscv/dts/mt5824-evb.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 Metanoia Communications Inc. All rights reserved. + */ +/dts-v1/; + +#include "mt2824.dtsi" + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Metanoia MT5824 EVB"; + compatible = "metanoia,mt5824-evb", "metanoia,mt2824"; + + chosen { + stdout-path = "uart0:115200n8"; + }; + + ddr: memory@0 { + device_type = "memory"; + reg = <0x0 0x0000000080000000 0x00000000 0x80000000>, + <0x1 0x0000000000000000 0x00000000 0x80000000>; + }; +}; + +&qspi { + flash@0 { + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <0x4>; + spi-tx-bus-width = <0x4>; + spi-max-frequency = <100000000>; + reg = <0x0>; + }; +}; -- 2.55.0
