From: Jun Chang <[email protected]> Add the ANDES_ERRATA_35102 config option to control the workaround for Andes CPU erratum #35102. When enabled, non-blocking load is disabled in the MMISC_CTL register during harts_early_init() to prevent potential data corruption.
Signed-off-by: Jun Chang <[email protected]> Signed-off-by: Benoît Monin <[email protected]> --- arch/riscv/cpu/andes/Kconfig | 3 +++ arch/riscv/cpu/andes/cpu.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/andes/Kconfig b/arch/riscv/cpu/andes/Kconfig index 120fec5e540..a2e68b6ad9c 100644 --- a/arch/riscv/cpu/andes/Kconfig +++ b/arch/riscv/cpu/andes/Kconfig @@ -15,3 +15,6 @@ config RISCV_ANDES help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. + +config ANDES_ERRATA_35102 + bool diff --git a/arch/riscv/cpu/andes/cpu.c b/arch/riscv/cpu/andes/cpu.c index d25ecba0e88..44704a2359e 100644 --- a/arch/riscv/cpu/andes/cpu.c +++ b/arch/riscv/cpu/andes/cpu.c @@ -57,7 +57,12 @@ void harts_early_init(void) } } - mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; + if (IS_ENABLED(CONFIG_ANDES_ERRATA_35102)) { + /* Errata #35102: Disable non-blocking load */ + mmisc_ctl_val &= ~MMISC_CTL_NON_BLOCKING_EN; + } else { + mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; + } csr_write(CSR_MMISC_CTL, mmisc_ctl_val); } -- 2.55.0
