Hi Tanmay, Thanks for the review. I've updated v2 patch 1/3 to keep the clock API return values in ulong and test IS_ERR_VALUE(). The missing-max-frequency path now checks clk_get_rate() before assigning it to cfg.f_max, rejects a zero rate, and preserves the clock API's error code.
I've retained your Reviewed-by on patches 2/3 and 3/3. Patch 2/3 now explains the intentional reversal of the driver's v9 single-block SPL policy and the MMC core's CMD12 path; its code is unchanged from v1. The revised three-patch stack replays cleanly on its exact base and passes checkpatch. Both R2S and RV2 configurations build successfully. With the separate DDR firmware overlap fix included, the combined firmware passed DDR initialization, FIT verification and automatic EFI/FreeBSD boot on the 2 GiB R2S and the 4 GiB RV2. These are combined-firmware warm-boot results, not isolated tests of this series. Cold boot of the corrected firmware, alternate cards, missing-frequency/error paths and error recovery remain untested. Thanks, Dave
