Take the target frequency of mtk_pll_calc_values() as a ulong instead of
a u32.
Clock rates are ulong, which is 64 bits on arm64, so a request above
4 GHz was silently truncated before the clamp to the PLL's fmax could
see it, and the PLL was programmed for whatever was left in the low 32
bits. Everything after the clamp already works in 64 bits.
Fixes: 0bd7dc74d2ff ("clk: MediaTek: add clock driver for MT7629 SoC.")
Signed-off-by: David Lechner <[email protected]>
---
drivers/clk/mediatek/clk-mtk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index af5a210073a..b3f4a07c8b9 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -512,7 +512,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_priv
*priv, u32 id,
* @freq: The desired target frequency
*/
static int mtk_pll_calc_values(struct mtk_clk_priv *priv, struct clk *clk,
- u32 *pcw, u32 *postdiv, u32 freq)
+ u32 *pcw, u32 *postdiv, ulong freq)
{
const struct mtk_pll_data *pll;
const struct mtk_parent *parent = &priv->tree->pll_parent;
--
2.53.0
