Return the rate the PLL ends up at from set_rate instead of 0, and make
the MT7629 and MT8516 early PLL setup check the result with
IS_ERR_VALUE().
The clk_ops set_rate() contract is to return the new rate on success,
but the PLL returned 0, and the two early PLL setups had come to treat
any other value as an error. mtk_pll_get_rate() moves above set_rate so
it can be used to read the rate back.
Fixes: 0bd7dc74d2ff ("clk: MediaTek: add clock driver for MT7629 SoC.")
Signed-off-by: David Lechner <[email protected]>
---
arch/arm/mach-mediatek/mt7629/init.c | 8 +++++---
arch/arm/mach-mediatek/mt8516/init.c | 8 +++++---
drivers/clk/mediatek/clk-mtk.c | 38 ++++++++++++++++++------------------
3 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-mediatek/mt7629/init.c
b/arch/arm/mach-mediatek/mt7629/init.c
index d12eb5339e9..193d4cb176e 100644
--- a/arch/arm/mach-mediatek/mt7629/init.c
+++ b/arch/arm/mach-mediatek/mt7629/init.c
@@ -16,6 +16,7 @@
#include <asm/sections.h>
#include <dm/uclass.h>
#include <linux/bitops.h>
+#include <linux/err.h>
#include <linux/io.h>
#include <dt-bindings/clock/mt7629-clk.h>
@@ -38,6 +39,7 @@ static int mtk_pll_early_init(void)
[CLK_APMIXED_SGMIPLL] = 650000000,
};
struct udevice *dev;
+ ulong rate;
int ret, i;
ret = uclass_get_device_by_driver(UCLASS_CLK,
@@ -49,9 +51,9 @@ static int mtk_pll_early_init(void)
for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
struct clk clk = { .id = i, .dev = dev };
- ret = clk_set_rate(&clk, pll_rates[i]);
- if (ret)
- return ret;
+ rate = clk_set_rate(&clk, pll_rates[i]);
+ if (IS_ERR_VALUE(rate))
+ return rate;
ret = clk_enable(&clk);
if (ret)
diff --git a/arch/arm/mach-mediatek/mt8516/init.c
b/arch/arm/mach-mediatek/mt8516/init.c
index 99574c14822..6427df10a91 100644
--- a/arch/arm/mach-mediatek/mt8516/init.c
+++ b/arch/arm/mach-mediatek/mt8516/init.c
@@ -19,6 +19,7 @@
#include <dm/ofnode.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8516-clk.h>
+#include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,7 @@ static int mtk_pll_early_init(void)
[CLK_APMIXED_MMPLL] = 380000000,
};
struct udevice *dev;
+ ulong rate;
ofnode node;
int ret, i;
@@ -54,9 +56,9 @@ static int mtk_pll_early_init(void)
for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
struct clk clk = { .id = i, .dev = dev };
- ret = clk_set_rate(&clk, pll_rates[i]);
- if (ret)
- return ret;
+ rate = clk_set_rate(&clk, pll_rates[i]);
+ if (IS_ERR_VALUE(rate))
+ return rate;
ret = clk_enable(&clk);
if (ret)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index b3f4a07c8b9..dd2d7e4e755 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -547,25 +547,6 @@ static int mtk_pll_calc_values(struct mtk_clk_priv *priv,
struct clk *clk,
return 0;
}
-static ulong mtk_clk_set_rate(struct clk *clk, ulong rate)
-{
- struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
- u32 pcw = 0;
- u32 postdiv;
- int ret;
-
- if (!mtk_clk_id_is_pll(priv->tree, clk->id))
- return -EINVAL;
-
- ret = mtk_pll_calc_values(priv, clk, &pcw, &postdiv, rate);
- if (ret)
- return ret;
-
- mtk_pll_set_rate_regs(priv, clk->id, pcw, postdiv);
-
- return 0;
-}
-
static ulong mtk_pll_get_rate(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
@@ -592,6 +573,25 @@ static ulong mtk_pll_get_rate(struct clk *clk)
return __mtk_pll_recalc_rate(pll, xtal_rate, pcw, postdiv);
}
+static ulong mtk_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 pcw = 0;
+ u32 postdiv;
+ int ret;
+
+ if (!mtk_clk_id_is_pll(priv->tree, clk->id))
+ return -EINVAL;
+
+ ret = mtk_pll_calc_values(priv, clk, &pcw, &postdiv, rate);
+ if (ret)
+ return ret;
+
+ mtk_pll_set_rate_regs(priv, clk->id, pcw, postdiv);
+
+ return mtk_pll_get_rate(clk);
+}
+
static int mtk_pll_enable(struct mtk_clk_priv *priv,
const struct mtk_pll_data *pll)
{
--
2.53.0
