Describe the vdosys0 display path: the display mutex, the two overlays and RDMAs, the DSI controller and its MIPI D-PHY, the two display PWMs driving panel backlights, the two display SMI larbs with the smi_common block behind them, and the multimedia IOMMU the larbs hang off.
The nodes follow the in-flight MT8189 device tree, so the overlays and RDMAs name their M4U port through the iommus property and the larbs carry mediatek,larb-id, which is how the display components find the larb to enable. Only the two display larbs are listed in the IOMMU's mediatek,larbs, since the other eleven belong to blocks U-Boot does not drive. The aliases are the ones the DSI driver uses to reach the pipeline components, matching what mt8366.dtsi already provides. Everything is disabled here and enabled by the boards that have a panel. Signed-off-by: David Lechner <[email protected]> --- arch/arm/dts/mt8189.dtsi | 147 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi index 656f5488c72..22c1c7761f1 100644 --- a/arch/arm/dts/mt8189.dtsi +++ b/arch/arm/dts/mt8189.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/memory/mediatek,mt8189-memory-port.h> #include <dt-bindings/power/mediatek,mt8189-power.h> #include <dt-bindings/reset/ti-syscon.h> @@ -18,6 +19,12 @@ #size-cells = <2>; aliases { + dsi0 = &dsi0; + mutex0 = &mutex0; + ovl0 = &disp_ovl0_4l; + ovl1 = &disp_ovl1_4l; + rdma0 = &disp_rdma0; + rdma1 = &disp_rdma1; serial0 = &uart0; }; @@ -776,5 +783,145 @@ reg = <0 0x1c012000 0 0x1000>; #clock-cells = <1>; }; + + disp_pwm0: pwm@1100e000 { + compatible = "mediatek,mt8189-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; + #pwm-cells = <2>; + clocks = <&pericfg_ao_clk CLK_PERAO_DISP_PWM0>, + <&topckgen_clk CLK_TOP_DISP_PWM_SEL>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + disp_pwm1: pwm@1100f000 { + compatible = "mediatek,mt8189-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; + #pwm-cells = <2>; + clocks = <&pericfg_ao_clk CLK_PERAO_DISP_PWM1>, + <&topckgen_clk CLK_TOP_DISP_PWM_SEL>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + mipi_tx_config0: dsi-phy@11b40000 { + compatible = "mediatek,mt8189-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11b40000 0 0x1000>; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + status = "disabled"; + }; + + mutex0: mutex@14001000 { + compatible = "mediatek,mt8189-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + status = "disabled"; + }; + + disp_ovl0_4l: ovl@14002000 { + compatible = "mediatek,mt8189-disp-ovl"; + reg = <0 0x14002000 0 0x1000>; + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + iommus = <&mm_iommu M4U_L0_P1_DISP_OVL0_4L_RDMA0>; + clocks = <&mmsys CLK_MM_DISP_OVL0_4L>; + status = "disabled"; + }; + + disp_ovl1_4l: ovl@14003000 { + compatible = "mediatek,mt8189-disp-ovl"; + reg = <0 0x14003000 0 0x1000>; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + iommus = <&mm_iommu M4U_L1_P1_DISP_OVL1_4L_RDMA0>; + clocks = <&mmsys CLK_MM_DISP_OVL1_4L>; + status = "disabled"; + }; + + disp_rdma0: rdma@14006000 { + compatible = "mediatek,mt8189-disp-rdma", "mediatek,mt8195-disp-rdma"; + reg = <0 0x14006000 0 0x1000>; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + iommus = <&mm_iommu M4U_L0_P5_DISP_RDMA0>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + status = "disabled"; + }; + + disp_rdma1: rdma@14007000 { + compatible = "mediatek,mt8189-disp-rdma", "mediatek,mt8195-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + iommus = <&mm_iommu M4U_L1_P5_DISP_RDMA1>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + status = "disabled"; + }; + + dsi0: dsi@14016000 { + compatible = "mediatek,mt8189-dsi"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + phys = <&mipi_tx_config0>; + phy-names = "dphy"; + clocks = <&mmsys CLK_MMSYS_0_DISP_DSI0>, + <&mmsys CLK_MMSYS_1_DISP_DSI0>, + <&mipi_tx_config0>; + clock-names = "engine", "digital", "hs"; + status = "disabled"; + }; + + smi_larb0: larb@1401c000 { + compatible = "mediatek,mt8189-smi-larb"; + reg = <0 0x1401c000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_LARB>, + <&mmsys CLK_MM_SMI_LARB>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + mediatek,larb-id = <SMI_L0_ID>; + mediatek,smi = <&smi_disp_common>; + status = "disabled"; + }; + + smi_larb1: larb@1401d000 { + compatible = "mediatek,mt8189-smi-larb"; + reg = <0 0x1401d000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_LARB>, + <&mmsys CLK_MM_SMI_LARB>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + mediatek,larb-id = <SMI_L1_ID>; + mediatek,smi = <&smi_disp_common>; + status = "disabled"; + }; + + smi_disp_common: smi@1e801000 { + compatible = "mediatek,mt8189-smi-common"; + reg = <0 0x1e801000 0 0x1000>; + clocks = <&mminfra_config_clk CLK_MMINFRA_SMI>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + status = "disabled"; + }; + + mm_iommu: iommu@1e802000 { + compatible = "mediatek,mt8189-iommu-mm"; + reg = <0 0x1e802000 0 0x5000>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names = "bclk"; + #iommu-cells = <1>; + mediatek,larbs = <&smi_larb0>, <&smi_larb1>; + power-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + }; }; }; -- 2.53.0
