The 1x100GE + 4x25G split of SerDes 1 is in next since v1, commit
035d68fc36b5 ("lx2160: add lx2160_serdes split and management").

This series builds on it with incremental patches to ease reviews,
but with many reworks:

- No more command that re-groups the lanes at the prompt: the MC has
  already started. Use hwconfig
- hwconfig values are named based on needed cases:
  serdes1:split becomes serdes1:100g4x25g (patch 2)
- Use a table (patches 3 to 5), and enter a mode through the one it
  starts from (patch 9)
- One patch per new mode: 2x40GE, 1x40GE + 4x10G and 1x100GE + 4x10G
- Rewrite documentation
- Add and apply to nbxv3

It is now mainly tested on a Nodebox v3
  setenv hwconfig serdes1:<mode>
  saveenv
  reset

- print checks using lx2160_serdes status 1
- in Linux, with the matching MC DPC, DPL: each case has its netdevices

As agreed with Tom on v4, the conversion of README.soc and
README.fsl-hwconfig to rST will be a separate series, after this one.

v6: https://lore.kernel.org/u-boot/[email protected]/
v5: https://lore.kernel.org/u-boot/[email protected]/
v4: https://lore.kernel.org/u-boot/[email protected]/
v3: https://lore.kernel.org/u-boot/[email protected]/
v2: https://lore.kernel.org/u-boot/[email protected]/

Changes in v7:
- rebased on next
- 8/13, 9/13: Reviewed-by from Vladimir
- 10/13, 11/13: reset only LNE-LNH (Vladimir), Reviewed-by of 11/13 dropped
- 12/13: 2x40g from protocol 13 or 20, one column per dpmac,
  follow the lane order of the RM for the mode names (Vladimir)

Changes in v6:
- 3/13, 4/13, 5/13, 6/13, 11/13: Reviewed-by from Vladimir
- 8/13: 40GE needs PLLS, only 161.1328125 MHz PLLS reference clock is supported 
(Vladimir)
- 12/13: same for the PLLS reference clock (Vladimir)

Changes in v5:
- 1/13, 2/13, 7/13, 13/13: Reviewed-by from Vladimir
- 3/13 (new): rename SPLIT_POLL_US to SRDS_POLL_US
- 4/13 (new): halt and reset of SD1 become helpers
- 5/13: the table only
- 6/13: report an unknown serdes1 value
- 9/13 (new): enter a mode through the one it starts from
- 10/13: skip logic of the reset added
- 12/13: reworded, PLLS reference clock, no list of boards

Changes in v4:
- rebased on next, incremental over v1 instead of replacing it
- 1/10 (new): drop `lx2160_serdes split`
- 2/10 (new): rename serdes1:split to serdes1:100g4x25g
- 3/10 (new): use a table to set SD1
- 4/10 (new): report invalid serdes1 names
- 5/10 (new): refuse once the MC runs
- 6/10, 7/10, 8/10: resp. v3 2/5, 3/5, 4/5: add other modes
- 9/10: v3 5/5, rewritten doc
- 10/10 (new): apply sd1 for the nbxv3

Vincent Jardin (13):
  board: lx2160a: serdes: drop the split subcommand
  board: lx2160a: serdes: rename serdes1:split to serdes1:100g4x25g
  board: lx2160a: serdes: rename SPLIT_POLL_US to SRDS_POLL_US
  board: lx2160a: serdes: move the SD1 halt and reset into helpers
  board: lx2160a: serdes: set SD1 with a table
  board: lx2160a: serdes: report unknown SD1 cases
  board: lx2160a: serdes: no SD1 config once MC runs
  board: lx2160a: serdes: add serdes1:2x40g
  board: lx2160a: serdes: enter a SD1 mode through the mode it starts
    from
  board: lx2160a: serdes: add serdes1:40g4x10g
  board: lx2160a: serdes: add serdes1:100g4x10g
  doc: lx2160a: document the sd1 hwconfig option
  board: nbxv3: apply sd1 hwconfig before MC starts

 .../cpu/armv8/fsl-layerscape/doc/README.soc   |   7 +
 board/nxp/lx2160a/eth_lx2160aqds.c            |   4 +-
 board/nxp/lx2160a/nbxv3/eth_nbxv3.c           |   3 +
 board/nxp/lx2160a/serdes_split.c              | 532 ++++++++++++++----
 board/nxp/lx2160a/serdes_split.h              |  16 +-
 doc/README.fsl-hwconfig                       |  70 +++
 6 files changed, 521 insertions(+), 111 deletions(-)

---
base-commit: ed869863c7e2aca50d57a05d843830dd843138c4
branch: for-upstream/lx2160a-serdes1-v7

-- 
2.43.0

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