Apple's M3 Pro (t6030) and Max (t6031 and t6034) SoCs are similar to
their M1 and M2 predecessors. The MMIO blocks have been extended but
M3 Pro and M3 Max still share the same overall layout although they
aren't as similar as M1/M2 Pro and Max.
Most of u-boot's existing drivers are compatible with the hardware and
M3 Pro and Max device trees will carry "apple,t8103-*" as fallback
compatible strings. Only apple-atcphy-reset will use a new compatible
due to USB4 and DisplayPort changes relevant to the Linux driver.

Signed-off-by: Janne Grunau <[email protected]>
---
 arch/arm/mach-apple/board.c | 97 +++++++++++++++++++++++++++++++++++++++++++++
 doc/board/apple/m1.rst      |  6 +++
 2 files changed, 103 insertions(+)

diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index e74a5a76919a..bd0c69fcb512 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -750,6 +750,99 @@ static struct mm_region t8122_mem_map[] = {
        }
 };
 
+/* Apple M3 Pro and Max */
+
+static struct mm_region t6030_mem_map[] = {
+       {
+               /* I/O */
+               .virt = 0x280000000,
+               .phys = 0x280000000,
+               .size = 2UL * SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* I/O */
+               .virt = 0x300000000,
+               .phys = 0x300000000,
+               .size = 3UL * SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* PCIE */
+               .virt = 0x580000000,
+               .phys = 0x580000000,
+               .size = SZ_512M,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* PCIE */
+               .virt = 0x5a0000000,
+               .phys = 0x5a0000000,
+               .size = SZ_512M,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+                        PTE_BLOCK_INNER_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* PCIE */
+               .virt = 0x5c0000000,
+               .phys = 0x5c0000000,
+               .size = SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+                        PTE_BLOCK_INNER_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* I/O ATC0 */
+               .virt = 0x700000000,
+               .phys = 0x700000000,
+               .size = SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* I/O ATC1 */
+               .virt = 0xb00000000,
+               .phys = 0xb00000000,
+               .size = SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* I/O ATC2 */
+               .virt = 0xf00000000,
+               .phys = 0xf00000000,
+               .size = SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* I/O ATC3 */
+               .virt = 0x1300000000,
+               .phys = 0x1300000000,
+               .size = SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* RAM */
+               .virt = 0x10000000000,
+               .phys = 0x10000000000,
+               .size = 16UL * SZ_1G,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               /* Framebuffer */
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+                        PTE_BLOCK_INNER_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
 struct mm_region *mem_map;
 
 int board_init(void)
@@ -799,6 +892,10 @@ void build_mem_map(void)
                mem_map = t6022_mem_map;
        else if (of_machine_is_compatible("apple,t8122"))
                mem_map = t8122_mem_map;
+       else if (of_machine_is_compatible("apple,t6030") ||
+                of_machine_is_compatible("apple,t6031") ||
+                of_machine_is_compatible("apple,t6034"))
+               mem_map = t6030_mem_map;
        else
                panic("Unsupported SoC\n");
 
diff --git a/doc/board/apple/m1.rst b/doc/board/apple/m1.rst
index 4ed275f7ea8c..002f4926ed5e 100644
--- a/doc/board/apple/m1.rst
+++ b/doc/board/apple/m1.rst
@@ -16,6 +16,8 @@ the following SoCs work:
  - Apple M2 Pro SoC (t6020)
  - Apple M2 Max SoC (t6021)
  - Apple M2 Ultra SoC (t6022)
+ - Apple M3 Pro SoC (t6030)
+ - Apple M3 Max SoC (t6031 and t6034)
 
 On these SoCs the following hardware is supported:
 
@@ -87,3 +89,7 @@ supported SoCs.
      - 0x2a1200000
    * - M1 Pro/Max/Ultra (t6000/t6001/t6002) and M2 Pro/Max/Ultra 
(t6020/t6021/t6022)
      - 0x39b200000
+   * - M3 Pro (t6030)
+     - 0x289200000
+   * - M3 Max/Ultra (t6031/t6034/t6032)
+     - 0x391200000

-- 
2.55.0

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