Apple's M3 Ultra (t6032) SoC consists like its M1 and M2 predecessors of two M3 Max dies with an "UltraFusion" interconnect. Since it is only used in the Mac Studio the mem map does not need to duplicate all entries. Two of the USB4 / Thunderbolt complexes on the second die are unused. Only PCIe host controller on the first die is used directly. The PCIe IO on the second die is used internally to connect the NVMe controller with the NAND flash. Most of u-boot's existing drivers are compatible with the hardware and M3 Ultra device trees will carry "apple,t8103-*" as fallback compatible strings. Only apple-atcphy-reset will use a new compatible as M3 Ultra has ThunderBolt 5 / USB4v2 USB-C ports.
Signed-off-by: Janne Grunau <[email protected]> --- arch/arm/mach-apple/board.c | 127 ++++++++++++++++++++++++++++++++++++++++++++ doc/board/apple/m1.rst | 1 + 2 files changed, 128 insertions(+) diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index bd0c69fcb512..d8ad925a00e6 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -843,6 +843,131 @@ static struct mm_region t6030_mem_map[] = { } }; +/* Apple M3 Ultra */ + +static struct mm_region t6032_mem_map[] = { + { + /* I/O */ + .virt = 0x280000000, + .phys = 0x280000000, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x300000000, + .phys = 0x300000000, + .size = 3UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC0 */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC1 */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC2 */ + .virt = 0xf00000000, + .phys = 0xf00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC3 */ + .virt = 0x1300000000, + .phys = 0x1300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2280000000, + .phys = 0x2280000000, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2300000000, + .phys = 0x2300000000, + .size = 3UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC4 */ + .virt = 0x2700000000, + .phys = 0x2700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC5 */ + .virt = 0x2b00000000, + .phys = 0x2b00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 16UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map; int board_init(void) @@ -896,6 +1021,8 @@ void build_mem_map(void) of_machine_is_compatible("apple,t6031") || of_machine_is_compatible("apple,t6034")) mem_map = t6030_mem_map; + else if (of_machine_is_compatible("apple,t6032")) + mem_map = t6032_mem_map; else panic("Unsupported SoC\n"); diff --git a/doc/board/apple/m1.rst b/doc/board/apple/m1.rst index 002f4926ed5e..f1be55996b95 100644 --- a/doc/board/apple/m1.rst +++ b/doc/board/apple/m1.rst @@ -18,6 +18,7 @@ the following SoCs work: - Apple M2 Ultra SoC (t6022) - Apple M3 Pro SoC (t6030) - Apple M3 Max SoC (t6031 and t6034) + - Apple M3 Ultra SoC (t6032) On these SoCs the following hardware is supported: -- 2.55.0
