Hello Fide, On Wed, Oct 14, 2026 at 09:03:31AM +0200, Mehmet Fide wrote: [...] > Move the DDR controller setup into the DCD: the clock gates, PLL2 with > its PFD2 as the DDR clock, the DDR pads, the DDRMC and PHY registers in > the order the board code wrote them, the controller start and its > completion.
What are you doing is clear already from the code, but why are you doing it? What's the motivation for such a change? Francesco
