From: Mehmet Fide <[email protected]> The ROM copies the whole image into the on-chip graphics RAM and runs it there. On the VF61 the L2 data array takes the upper half of that RAM, so the image has to stay under 480 KB, and the board sits a few KB below the limit. The i.MX6 boards without SPL let the ROM bring the DDR up from the Device Configuration Data in the image header and load U-Boot straight into DDR. The Vybrid ROM reads the same DCD (VFxxxRM rev. 8, 7.5.6.2); this board brought the DDR up in C instead, from the RAM the ROM had copied it to.
Move the DDR controller setup into the DCD: the clock gates, PLL2 with its PFD2 as the DDR clock, the DDR pads, the DDRMC and PHY registers in the order the board code wrote them, the controller start and its completion. The entries are a trace of the register writes the C sequence made, so the values are the ones Toradex validated. The DDR clock comes from PLL2 PFD2 on both modules; the VF50 took it from the system clock before, at the same 396 MHz. U-Boot links at 0x87800000, inside the 128 MB of the VF50, and the size limit goes away. Tested on a Colibri VF50 V1.2A and a Colibri VF61 V1.2B: the ROM loads U-Boot into DDR, a 3 MiB mtest passes, UBI attaches and Linux boots from NAND on both modules. Signed-off-by: Mehmet Fide <[email protected]> --- Notes: The DCD entries come from a trace of the register writes the C sequence made on the VF61 (every writel in ddrmc_ctrl_init_ddr3, the DDR pads the pinctrl driver set and the clock bits the DDR needs), so no value was typed by hand. The VF50 trace differs only in the clock selection, which the DCD makes the same on both. Read back after the DCD boot: CCM_CCSR 0x0003ff24 (VF50) and 0x0001ff24 (VF61), DDRC_CLK_SEL 0 on both; ANADIG_PLL2_CTRL 0x80002001 (locked); DDRMC CR80 0x11000000; relocation offset 0x00783000 (VF50) and 0x08783000 (VF61) from 0x87800000. A 1.06 MB build of the same tree (EFI with secure boot, bootstd, more file systems and compressors), larger than the whole on-chip RAM of the VF50, boots from NAND the same way and reaches Linux. The generator that turns such a trace into the cfg lines is not part of the patch; the cfg is the result. board/toradex/colibri_vf/colibri_vf.c | 131 ++------------------- board/toradex/colibri_vf/imximage.cfg | 158 ++++++++++++++++++++++++++ configs/colibri_vf_defconfig | 4 +- 3 files changed, 166 insertions(+), 127 deletions(-) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 87f82396d63..adf755707f9 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -11,7 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> -#include <asm/arch/ddrmc-vf610.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux-vf610.h> #include <asm/gpio.h> @@ -29,120 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; #define PTC0_GPIO_45 45 -static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { - { DDRMC_CR79_CTLUPD_AREF(1), 79 }, - /* sets manual values for read lvl. (gate) delay of data slice 0/1 */ - { DDRMC_CR105_RDLVL_DL_0(28), 105 }, - { DDRMC_CR106_RDLVL_GTDL_0(24), 106 }, - { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 }, - { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 }, - - /* AXI */ - { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, - { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, - { DDRMC_CR120_AXI0_PRI1_RPRI(2) | - DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, - { DDRMC_CR121_AXI0_PRI3_RPRI(2) | - DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, - { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | - DDRMC_CR122_AXI0_PRIRLX(100), 122 }, - { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | - DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, - { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, - { DDRMC_CR126_PHY_RDLAT(8), 126 }, - { DDRMC_CR132_WRLAT_ADJ(5) | - DDRMC_CR132_RDLAT_ADJ(6), 132 }, - { DDRMC_CR137_PHYCTL_DL(2), 137 }, - { DDRMC_CR138_PHY_WRLV_MXDL(256) | - DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, - { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | - DDRMC_CR139_PHY_WRLV_DLL(3) | - DDRMC_CR139_PHY_WRLV_EN(3), 139 }, - { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, - { DDRMC_CR143_RDLV_GAT_MXDL(1536) | - DDRMC_CR143_RDLV_MXDL(128), 143 }, - { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | - DDRMC_CR144_PHY_RDLV_DLL(3) | - DDRMC_CR144_PHY_RDLV_EN(3), 144 }, - { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, - { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, - { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, - { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, - { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | - DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, - - { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1) | - DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | - DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, - { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 }, - { DDRMC_CR158_TWR(6), 158 }, - { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | - DDRMC_CR161_TODTH_WR(2), 161 }, - /* end marker */ - { 0, -1 } -}; - int dram_init(void) { - static const struct ddr3_jedec_timings timings = { - .tinit = 5, - .trst_pwron = 80000, - .cke_inactive = 200000, - .wrlat = 5, - .caslat_lin = 12, - .trc = 21, - .trrd = 4, - .tccd = 4, - .tbst_int_interval = 0, - .tfaw = 20, - .trp = 6, - .twtr = 4, - .tras_min = 15, - .tmrd = 4, - .trtp = 4, - .tras_max = 28080, - .tmod = 12, - .tckesr = 4, - .tcke = 3, - .trcd_int = 6, - .tras_lockout = 0, - .tdal = 12, - .bstlen = 3, - .tdll = 512, /* not applicable since freq. scaling - * is not used - */ - .trp_ab = 6, - .tref = 3120, - .trfc = 64, - .tref_int = 0, - .tpdex = 3, - .txpdll = 10, - .txsnr = 68, /* changed to conform to JEDEC - * specifications - */ - .txsr = 506, /* changed to conform to JEDEC - * specifications - */ - .cksrx = 5, - .cksre = 5, - .freq_chg_en = 0, - .zqcl = 256, - .zqinit = 512, - .zqcs = 64, - .ref_per_zq = 64, - .zqcs_rotate = 0, - .aprebit = 10, - .cmd_age_cnt = 64, - .age_cnt = 64, - .q_fullness = 7, - .odt_rd_mapcs0 = 0, - .odt_wr_mapcs0 = 1, - .wlmrd = 40, - .wldqsen = 25, - }; - - ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; @@ -263,12 +150,10 @@ static void clock_init(void) ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | ANADIG_PLL5_CTRL_DIV_SELECT); - if (is_colibri_vf61()) { - clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | - ANADIG_PLL2_CTRL_POWERDOWN, - ANADIG_PLL2_CTRL_ENABLE | - ANADIG_PLL2_CTRL_DIV_SELECT); - } + clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | + ANADIG_PLL2_CTRL_POWERDOWN, + ANADIG_PLL2_CTRL_ENABLE | + ANADIG_PLL2_CTRL_DIV_SELECT); clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); @@ -277,13 +162,11 @@ static void clock_init(void) CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); /* See "Typical PLL Configuration" */ - if (is_colibri_vf61()) { + if (is_colibri_vf61()) pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1); - ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); - } else { + else pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3); - ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1); - } + ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | diff --git a/board/toradex/colibri_vf/imximage.cfg b/board/toradex/colibri_vf/imximage.cfg index 7e629d2f9e7..017fa8c3d13 100644 --- a/board/toradex/colibri_vf/imximage.cfg +++ b/board/toradex/colibri_vf/imximage.cfg @@ -14,3 +14,161 @@ IMAGE_VERSION 2 /* Boot Offset 0x400, valid for both SD and NAND boot */ BOOT_OFFSET FLASH_OFFSET_STANDARD + +/* + * Device Configuration Data: the ROM runs the DDR controller up before it + * loads the image into DDR. Clock gates, PLL2 with its PFD2 as the DDR + * clock, the DDR pads, the DDRMC and PHY registers in the order the board + * code wrote them, then the controller start and its completion. + */ +SET_BIT 4 0x4006b048 0x00030000 /* IOMUXC clock */ +SET_BIT 4 0x4006b04c 0x00000003 /* ANADIG clock */ +SET_BIT 4 0x4006b058 0x30000000 /* DDRMC clock */ +CLR_BIT 4 0x40050030 0x00011000 /* PLL2: no bypass, no power down */ +SET_BIT 4 0x40050030 0x00002001 /* PLL2: enable, 528 MHz */ +CHECK_BITS_SET 4 0x40050030 0x80000000 /* PLL2 lock */ +SET_BIT 4 0x4006b008 0x00002000 /* PLL2 PFD2 enable */ +CLR_BIT 4 0x4006b008 0x00000040 /* DDRC clock from PLL2 PFD2 */ +DATA 4 0x40048220 0x00000180 /* DDR pad 0x220 */ +DATA 4 0x40048224 0x00000180 /* DDR pad 0x224 */ +DATA 4 0x40048228 0x00000180 /* DDR pad 0x228 */ +DATA 4 0x4004822c 0x00000180 /* DDR pad 0x22c */ +DATA 4 0x40048230 0x00000180 /* DDR pad 0x230 */ +DATA 4 0x40048234 0x00000180 /* DDR pad 0x234 */ +DATA 4 0x40048238 0x00000180 /* DDR pad 0x238 */ +DATA 4 0x4004823c 0x00000180 /* DDR pad 0x23c */ +DATA 4 0x40048240 0x00000180 /* DDR pad 0x240 */ +DATA 4 0x40048244 0x00000180 /* DDR pad 0x244 */ +DATA 4 0x40048248 0x00000180 /* DDR pad 0x248 */ +DATA 4 0x4004824c 0x00000180 /* DDR pad 0x24c */ +DATA 4 0x40048250 0x00000180 /* DDR pad 0x250 */ +DATA 4 0x40048254 0x00000180 /* DDR pad 0x254 */ +DATA 4 0x40048258 0x00000180 /* DDR pad 0x258 */ +DATA 4 0x4004825c 0x00000180 /* DDR pad 0x25c */ +DATA 4 0x40048260 0x00000180 /* DDR pad 0x260 */ +DATA 4 0x40048264 0x00000180 /* DDR pad 0x264 */ +DATA 4 0x40048268 0x00000180 /* DDR pad 0x268 */ +DATA 4 0x4004826c 0x00000180 /* DDR pad 0x26c */ +DATA 4 0x40048270 0x00000180 /* DDR pad 0x270 */ +DATA 4 0x40048274 0x00000180 /* DDR pad 0x274 */ +DATA 4 0x40048278 0x00000180 /* DDR pad 0x278 */ +DATA 4 0x4004827c 0x00010180 /* DDR pad 0x27c */ +DATA 4 0x40048280 0x00010180 /* DDR pad 0x280 */ +DATA 4 0x40048284 0x00010180 /* DDR pad 0x284 */ +DATA 4 0x40048288 0x00010180 /* DDR pad 0x288 */ +DATA 4 0x4004828c 0x00010180 /* DDR pad 0x28c */ +DATA 4 0x40048290 0x00010180 /* DDR pad 0x290 */ +DATA 4 0x40048294 0x00010180 /* DDR pad 0x294 */ +DATA 4 0x40048298 0x00010180 /* DDR pad 0x298 */ +DATA 4 0x4004829c 0x00010180 /* DDR pad 0x29c */ +DATA 4 0x400482a0 0x00010180 /* DDR pad 0x2a0 */ +DATA 4 0x400482a4 0x00010180 /* DDR pad 0x2a4 */ +DATA 4 0x400482a8 0x00010180 /* DDR pad 0x2a8 */ +DATA 4 0x400482ac 0x00010180 /* DDR pad 0x2ac */ +DATA 4 0x400482b0 0x00010180 /* DDR pad 0x2b0 */ +DATA 4 0x400482b4 0x00010180 /* DDR pad 0x2b4 */ +DATA 4 0x400482b8 0x00010180 /* DDR pad 0x2b8 */ +DATA 4 0x400482bc 0x00010180 /* DDR pad 0x2bc */ +DATA 4 0x400482c0 0x00010180 /* DDR pad 0x2c0 */ +DATA 4 0x400482c4 0x00010180 /* DDR pad 0x2c4 */ +DATA 4 0x400482c8 0x00010180 /* DDR pad 0x2c8 */ +DATA 4 0x400482cc 0x00000180 /* DDR pad 0x2cc */ +DATA 4 0x400482d0 0x00000180 /* DDR pad 0x2d0 */ +DATA 4 0x400482d4 0x00000180 /* DDR pad 0x2d4 */ +DATA 4 0x400482d8 0x00000180 /* DDR pad 0x2d8 */ +DATA 4 0x400482dc 0x00000180 /* DDR pad 0x2dc */ +DATA 4 0x400482e0 0x00000180 /* DDR pad 0x2e0 */ +DATA 4 0x4004821c 0x00000180 /* DDR pad 0x21c */ +DATA 4 0x400ae000 0x00000600 /* CR0 */ +DATA 4 0x400ae008 0x00000005 /* CR2 */ +DATA 4 0x400ae028 0x00013880 /* CR10 */ +DATA 4 0x400ae02c 0x00030d40 /* CR11 */ +DATA 4 0x400ae030 0x0000050c /* CR12 */ +DATA 4 0x400ae034 0x15040400 /* CR13 */ +DATA 4 0x400ae038 0x1406040f /* CR14 */ +DATA 4 0x400ae040 0x04040000 /* CR16 */ +DATA 4 0x400ae044 0x006db00c /* CR17 */ +DATA 4 0x400ae048 0x00000403 /* CR18 */ +DATA 4 0x400ae050 0x01000000 /* CR20 */ +DATA 4 0x400ae054 0x00060001 /* CR21 */ +DATA 4 0x400ae058 0x000c0000 /* CR22 */ +DATA 4 0x400ae05c 0x03000200 /* CR23 */ +DATA 4 0x400ae060 0x00000006 /* CR24 */ +DATA 4 0x400ae064 0x00010000 /* CR25 */ +DATA 4 0x400ae068 0x0c300040 /* CR26 */ +DATA 4 0x400ae070 0x00000000 /* CR28 */ +DATA 4 0x400ae074 0x00000003 /* CR29 */ +DATA 4 0x400ae078 0x0000000a /* CR30 */ +DATA 4 0x400ae07c 0x004401fa /* CR31 */ +DATA 4 0x400ae084 0x00010000 /* CR33 */ +DATA 4 0x400ae088 0x00050500 /* CR34 */ +DATA 4 0x400ae098 0x00000000 /* CR38 */ +DATA 4 0x400ae09c 0x04001002 /* CR39 */ +DATA 4 0x400ae0a4 0x00000001 /* CR41 */ +DATA 4 0x400ae0c0 0x00460420 /* CR48 */ +DATA 4 0x400ae108 0x01000200 /* CR66 */ +DATA 4 0x400ae10c 0x00000040 /* CR67 */ +DATA 4 0x400ae114 0x00000200 /* CR69 */ +DATA 4 0x400ae118 0x00000040 /* CR70 */ +DATA 4 0x400ae120 0x00000000 /* CR72 */ +DATA 4 0x400ae124 0x0a010200 /* CR73 */ +DATA 4 0x400ae128 0x01014040 /* CR74 */ +DATA 4 0x400ae12c 0x01010101 /* CR75 */ +DATA 4 0x400ae130 0x03030100 /* CR76 */ +DATA 4 0x400ae134 0x01000101 /* CR77 */ +DATA 4 0x400ae138 0x0700000c /* CR78 */ +DATA 4 0x400ae148 0x10000000 /* CR82 */ +DATA 4 0x400ae15c 0x01000000 /* CR87 */ +DATA 4 0x400ae160 0x00040000 /* CR88 */ +DATA 4 0x400ae164 0x00000002 /* CR89 */ +DATA 4 0x400ae16c 0x00020000 /* CR91 */ +DATA 4 0x400ae180 0x00002819 /* CR96 */ +DATA 4 0x400ae13c 0x01000000 /* CR79 */ +DATA 4 0x400ae1a4 0x00001c00 /* CR105 */ +DATA 4 0x400ae1a8 0x00000018 /* CR106 */ +DATA 4 0x400ae1b8 0x0018001c /* CR110 */ +DATA 4 0x400ae198 0x00010100 /* CR102 */ +DATA 4 0x400ae1d4 0x00000000 /* CR117 */ +DATA 4 0x400ae1d8 0x01010000 /* CR118 */ +DATA 4 0x400ae1e0 0x02020000 /* CR120 */ +DATA 4 0x400ae1e4 0x00000202 /* CR121 */ +DATA 4 0x400ae1e8 0x01010064 /* CR122 */ +DATA 4 0x400ae1ec 0x00010101 /* CR123 */ +DATA 4 0x400ae1f0 0x00000064 /* CR124 */ +DATA 4 0x400ae1f8 0x00000800 /* CR126 */ +DATA 4 0x400ae210 0x00000506 /* CR132 */ +DATA 4 0x400ae224 0x00020000 /* CR137 */ +DATA 4 0x400ae228 0x01000100 /* CR138 */ +DATA 4 0x400ae22c 0x04070303 /* CR139 */ +DATA 4 0x400ae230 0x00000040 /* CR140 */ +DATA 4 0x400ae23c 0x06000080 /* CR143 */ +DATA 4 0x400ae240 0x04070303 /* CR144 */ +DATA 4 0x400ae244 0x00000040 /* CR145 */ +DATA 4 0x400ae248 0x00000040 /* CR146 */ +DATA 4 0x400ae24c 0x000f0000 /* CR147 */ +DATA 4 0x400ae250 0x000f0000 /* CR148 */ +DATA 4 0x400ae25c 0x00000101 /* CR151 */ +DATA 4 0x400ae268 0x682c4000 /* CR154 */ +DATA 4 0x400ae26c 0x00000012 /* CR155 */ +DATA 4 0x400ae278 0x00000006 /* CR158 */ +DATA 4 0x400ae284 0x00010202 /* CR161 */ +DATA 4 0x400ae400 0x00002613 /* PHY0 */ +DATA 4 0x400ae440 0x00002613 /* PHY16 */ +DATA 4 0x400ae480 0x00002613 /* PHY32 */ +DATA 4 0x400ae404 0x00002615 /* PHY1 */ +DATA 4 0x400ae444 0x00002615 /* PHY17 */ +DATA 4 0x400ae408 0x00210000 /* PHY2 */ +DATA 4 0x400ae448 0x00210000 /* PHY18 */ +DATA 4 0x400ae488 0x00210000 /* PHY34 */ +DATA 4 0x400ae40c 0x0001012a /* PHY3 */ +DATA 4 0x400ae44c 0x0001012a /* PHY19 */ +DATA 4 0x400ae48c 0x0001012a /* PHY35 */ +DATA 4 0x400ae410 0x00002000 /* PHY4 */ +DATA 4 0x400ae450 0x00002000 /* PHY20 */ +DATA 4 0x400ae490 0x00002000 /* PHY36 */ +DATA 4 0x400ae4c4 0x00000000 /* PHY49 */ +DATA 4 0x400ae4c8 0x00001100 /* PHY50 */ +DATA 4 0x400ae4d0 0x00010101 /* PHY52 */ +DATA 4 0x400ae000 0x00000601 /* CR0 */ +CHECK_BITS_SET 4 0x400ae140 0x00000100 /* CR80 init complete */ +DATA 4 0x400ae144 0x00000100 /* CR81 */ diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index beb64189d5c..fcff654e4e1 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y -CONFIG_TEXT_BASE=0x3f408000 +CONFIG_TEXT_BASE=0x87800000 CONFIG_SYS_MALLOC_LEN=0x0220000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 @@ -15,8 +15,6 @@ CONFIG_TARGET_COLIBRI_VF=y CONFIG_SYS_MEMTEST_START=0x80010000 CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_HAS_BOARD_SIZE_LIMIT=y -CONFIG_BOARD_SIZE_LIMIT=491520 # CONFIG_EFI_LOADER is not set CONFIG_BOOTDELAY=1 CONFIG_FDT_FIXUP_PARTITIONS=y -- 2.55.0
