On 12-10-2026 19:30, Kathpalia, Tanmay wrote: > Dave, I hope you are aligned with the changes discussed and tested. > Could you please post a new version incorporating them?
Hi Tanmay, Sorry for the slow reply. I'm moving my K1 boards to a different boot chain, oreboot plus EDK2, so I won't be respinning this series. Thanks to you, Zixian, Yixun and Anand for the testing and the careful review. Where things stand, for whoever picks it up: - 1/3: Yixun suggested a sane default max-frequency when the DT has none, rather than trusting what an earlier stage left behind, and asked for a clearer explanation than "happens to return 0". Hung-Chun's RFC, "[RFC PATCH 0/2] mmc: k1: do not require max-frequency in the device tree", covers the same ground. - 2/3: the BPI-F3 failure Zixian reported comes from set_vdd_mmc() putting the SD I/O rail at 1.8 V in SPL. With the rail at 3.3 V, Zixian and Yixun both see multi-block reads working in SPL. The agreed fix is to drop set_vdd_mmc() and enable CONFIG_SPL_MMC_IO_VOLTAGE and CONFIG_SPL_PINCTRL, so the driver sets the rail and pads itself. Anand's dtsi change adding vmmc-supply/vqmmc-supply for SPL would go with it. Both need to land before or with this patch. - 3/3: Yixun pointed out that clk-uclass counts enables, so the clock half doesn't hold. Only the reset half, where release() asserts the shared reset, may still be needed, and that needs a test or a reset-only version. Tanmay, Zixian, Hung-Chun: if any of you wants to take this over, please do. Keep or drop my authorship and Signed-off-by, whichever fits what you end up posting. Thanks, Dave
