Add the clock RCG, gate bit definitions, and frequency table needed
to enable and configure the SE0 (SPI) serial engine clock on QUPv3
wrapper 3, GCC_QUPV3_WRAP3_S0_CLK. This is required to bring up the
GENI SPI controller on QUPv3 wrapper 3, e.g. for SPI-NOR flash
attached to that wrapper.
Also add the wrapper's M-AHB/S-AHB clock gates, and the QSPI/AGGRE-NOC
gates that are auto-enabled alongside the SE0 clock.
The register offset, gate bits and frequency table are adapted from
the Linux GCC driver added in commit 08c51ceb12f7 ("clk: qcom: add
the GCC driver for sa8775p").
Reviewed-by: Balaji Selvanathan <[email protected]>
Signed-off-by: Vandhiadevan Karunamoorthy
<[email protected]>
---
Changes in v3:
- Mention the Linux commit the clock data is taken from
- Add Reviewed-by from Balaji
- Link to v2:
https://lore.kernel.org/u-boot/20261013-b4-sa8775p-qup3-spi-clk-v2-1-bd6365d81...@oss.qualcomm.com
---
drivers/clk/qcom/clock-sa8775p.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index a7bd6c43004..9ac914802a3 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -18,6 +18,7 @@
#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0x1b040
#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028
#define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c
+#define QUPV3_WRAP3_S0_CLK_CMD_RCGR 0xc4154
#define UFS_PHY_AXI_CLK_CMD_RCGR 0x8302c
#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x83074
@@ -50,7 +51,27 @@
#define GCC_QUPV3_WRAP2_S5_CLK_ENA_BIT BIT(9)
#define GCC_QUPV3_WRAP2_S6_CLK_ENA_BIT BIT(29)
+#define GCC_QUPV3_WRAP_3_S_AHB_ENA_BIT BIT(20)
#define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25)
+#define GCC_QUPV3_WRAP3_QSPI_ENA_BIT BIT(26)
+#define GCC_QUPV3_WRAP_3_M_AHB_ENA_BIT BIT(27)
+#define GCC_AGGRE_NOC_QUPV3_AXI_ENA_BIT BIT(28)
+
+/* QUP Wrapper 3 SE0 (SPI) clock frequency table */
+static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(48000000, CFG_CLK_SRC_GPLL0, 2, 4, 25),
+ F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+ F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ { }
+};
/* UFS AXI clock frequency table */
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
@@ -148,6 +169,12 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n,
freq->src, 8);
return freq->freq;
+ case GCC_QUPV3_WRAP3_S0_CLK:
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap3_s0_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP3_S0_CLK_CMD_RCGR,
+ freq->pre_div, freq->m, freq->n,
+ freq->src, 16);
+ return freq->freq;
default:
return 0;
}
@@ -190,7 +217,11 @@ static const struct gate_clk sa8775p_clks[] = {
GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x4b018,
GCC_QUPV3_WRAP2_S6_CLK_ENA_BIT),
/* QUP Wrapper 3 clocks */
+ GATE_CLK(GCC_QUPV3_WRAP_3_S_AHB_CLK, 0x4b000,
GCC_QUPV3_WRAP_3_S_AHB_ENA_BIT),
GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000,
GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT),
+ GATE_CLK(GCC_QUPV3_WRAP3_QSPI_CLK, 0x4b000,
GCC_QUPV3_WRAP3_QSPI_ENA_BIT),
+ GATE_CLK(GCC_QUPV3_WRAP_3_M_AHB_CLK, 0x4b000,
GCC_QUPV3_WRAP_3_M_AHB_ENA_BIT),
+ GATE_CLK(GCC_AGGRE_NOC_QUPV3_AXI_CLK, 0x4b000,
GCC_AGGRE_NOC_QUPV3_AXI_ENA_BIT),
/* UFS PHY clocks */
GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0), 0x83018),
@@ -230,6 +261,10 @@ static int sa8775p_enable(struct clk *clk)
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
break;
+ case GCC_QUPV3_WRAP3_S0_CLK:
+ qcom_gate_clk_en(priv, GCC_QUPV3_WRAP3_QSPI_CLK);
+ qcom_gate_clk_en(priv, GCC_AGGRE_NOC_QUPV3_AXI_CLK);
+ break;
}
return qcom_gate_clk_en(priv, clk->id);
---
base-commit: fed92546960a92177d67c0b8d7b22385f50fed29
change-id: 20260924-b4-sa8775p-qup3-spi-clk-6c01d31b33ea
Best regards,
--
Vandhiadevan Karunamoorthy <[email protected]>
