An Allwinner B288 e-reader. The DT is a copy of the one under review for Linux, until it can come from dts/upstream.
Signed-off-by: Pablo Mazzini <[email protected]> --- arch/arm/dts/Makefile | 2 + arch/arm/dts/sun8i-b288-pocketbook-verse.dts | 114 ++++++++ arch/arm/dts/sun8i-b288.dtsi | 292 +++++++++++++++++++ board/sunxi/MAINTAINERS | 6 + configs/pocketbook_verse_defconfig | 10 + 5 files changed, 424 insertions(+) create mode 100644 arch/arm/dts/sun8i-b288-pocketbook-verse.dts create mode 100644 arch/arm/dts/sun8i-b288.dtsi create mode 100644 configs/pocketbook_verse_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 099e3f082b6..039fbab2a90 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -586,6 +586,8 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb +dtb-$(CONFIG_MACH_SUN8I_B288) += \ + sun8i-b288-pocketbook-verse.dtb dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ diff --git a/arch/arm/dts/sun8i-b288-pocketbook-verse.dts b/arch/arm/dts/sun8i-b288-pocketbook-verse.dts new file mode 100644 index 00000000000..a60cbb63801 --- /dev/null +++ b/arch/arm/dts/sun8i-b288-pocketbook-verse.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * PocketBook Verse (PB629), an Allwinner B288 based e-reader. + */ + +/dts-v1/; +#include "sun8i-b288.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "PocketBook Verse"; + compatible = "pocketbook,verse", "allwinner,sun8i-b288"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dldo2>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pd-supply = <®_dldo1>; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + /* labelled AXP227 */ + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1260000>; + regulator-max-microvolt = <1260000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vcc-dram"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc"; +}; + +®_dldo2 { + /* microSD slot */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sdcv"; +}; diff --git a/arch/arm/dts/sun8i-b288.dtsi b/arch/arm/dts/sun8i-b288.dtsi new file mode 100644 index 00000000000..53832ea9dc0 --- /dev/null +++ b/arch/arm/dts/sun8i-b288.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Allwinner B288 (sun8iw10p1) SoC + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> +#include <dt-bindings/clock/sun8i-b288-ccu.h> +#include <dt-bindings/reset/sun8i-b288-ccu.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + osc24M: osc24M-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext-osc32k"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nmi_intc: interrupt-controller@1c000d0 { + compatible = "allwinner,sun8i-b288-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c000d0 0x0c>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* + * mmc0 is a v4p1x controller, so it runs in the old timing + * mode and needs the sample and output phase clocks. + */ + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-b288-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_SDMMC0_BUS>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-b288-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_SDMMC3_BUS>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + max-frequency = <150000000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* mmc2 @0x01c11000 is an unsupported SDHCI-style controller. */ + + ccu: clock-controller@1c20000 { + compatible = "allwinner,sun8i-b288-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rtc: rtc@1c20400 { + compatible = "allwinner,sun8i-b288-rtc"; + reg = <0x01c20400 0x400>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clock-output-names = "osc32k", "osc32k-out"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-b288-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + allwinner,pinmux = <2>; + drive-strength = <30>; + bias-pull-up; + }; + + i2c0_pins: i2c0-pins { + pins = "PB6", "PB7"; + function = "i2c0"; + allwinner,pinmux = <2>; + }; + + mmc3_pins: mmc3-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14"; + function = "mmc3"; + allwinner,pinmux = <5>; + drive-strength = <40>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB4", "PB5"; + function = "uart0"; + allwinner,pinmux = <2>; + }; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,sun8i-b288-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TWI0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TWI1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TWI2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index df745f14649..53fd2666f21 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -539,6 +539,12 @@ M: Arnaud Ferraris <[email protected]> S: Maintained F: configs/pinetab_defconfig +POCKETBOOK VERSE BOARD +M: Pablo Mazzini <[email protected]> +S: Maintained +F: arch/arm/dts/sun8i-b288* +F: configs/pocketbook_verse_defconfig + R16 EVB PARROT BOARD M: Quentin Schulz <[email protected]> S: Maintained diff --git a/configs/pocketbook_verse_defconfig b/configs/pocketbook_verse_defconfig new file mode 100644 index 00000000000..df86ab4b786 --- /dev/null +++ b/configs/pocketbook_verse_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-b288-pocketbook-verse" +CONFIG_DRAM_CLK=672 +CONFIG_SPL=y +CONFIG_MACH_SUN8I_B288=y +CONFIG_DRAM_ZQ=3881977 +# CONFIG_HAS_ARMV7_SECURE_BASE is not set +# CONFIG_OF_UPSTREAM is not set +CONFIG_NO_NET=y -- 2.52.0
