On 16/10/2026 12:40 pm, Chen Huei Lok wrote:
From: Tien Fong Chee <[email protected]>Enable self-refresh support in DDR4 for retaining DDR4 content with minimal power when reset is triggered. On a configuration reset with retention enabled, the trained PHY calibration data is restored from a backup instead of running a full calibration, so the DDR contents are preserved across the reset. The same INIT0.skip_dram_init / PWRCTL self-refresh entry settings that LPDDR4 requires are also applied to DDR4, as some DDR4 chips need them to enter and exit retention correctly. The backup calibration data is copied to DDR only when DDR retention is enabled, and the backup header length ('cal->header.data_len') is validated against the HPS handoff region so a corrupted or oversized value cannot overflow into the handoff data before it is consumed. Look up the DDR controller node using the "intel,sdr-ctl-n5x" compatible string so it matches the node defined in the device tree. Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Chen Huei Lok <[email protected]> --- .../include/mach/system_manager_soc64.h | 3 +- drivers/ddr/altera/sdram_n5x.c | 869 ++++++++++++++++-- 2 files changed, 790 insertions(+), 82 deletions(-)
[...] Reviewed-by: Tien Fong Chee <[email protected]> Best regards, Tien Fong
